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Showing papers on "Topology (electrical circuits) published in 1988"


Journal ArticleDOI
TL;DR: Design considerations are presented for attaining accurate output balancing in fully differential operational amplifiers over the useful operating frequency of the differential signals, and two circuit designs implemented in a 5-V, 1- mu m process are presented.
Abstract: Design considerations are presented for attaining accurate output balancing in fully differential operational amplifiers over the useful operating frequency of the differential signals. Such output balancing is obtained by merging the common-mode feedback and the differential gain paths as close to the front end of the amplifier as possible, ensuring maximum sharing of circuit components. Two circuit designs implemented in a 5-V, 1.75- mu m process are presented, one based on a two-stage topology and one based on a folded cascode topology. Experimental results for both designs are given. >

167 citations


Journal ArticleDOI
TL;DR: In this paper, a method for detecting topology errors in electric power networks is developed by providing a geometric interpretation of the measurement residuals caused by such errors, and an equation is developed for a matrix whose column linear dependencies determine topology error detectability and identifiability.
Abstract: A method for detecting topology errors in electric power networks is developed by providing a geometric interpretation of the measurement residuals caused by such errors. A test for single topology errors is presented that is similar to the normalized residuals test for measurement errors. This test is generalized to multiple topology errors. The concept of critical network branches (where their removal renders the network unobservable) is introduced and extended to critical-branch k-tuples. It is shown that topology errors on critical branches cannot be detected from measurement residuals. An equation is developed for a matrix whose column linear dependencies determine topology error detectability and identifiability. An example for an IEEE 14 bus network is provided. >

150 citations


Journal ArticleDOI
TL;DR: In this article, a power converter suitable for one-step conversion of the single-phase high-frequency link voltage to the three-phase low-frequency voltages typically required for interfacing with system sources and loads was proposed.
Abstract: A single-phase high-frequency link appears to be an attractive alternative to the DC link commonly used in power conversion systems. The authors propose a power converter suitable for one-step conversion of the single-phase high-frequency link voltage to the three-phase low-frequency voltages typically required for interfacing with system sources and loads. The converter utilizes zero voltage switching principles to minimize switching losses and uses an easy-to-implement technique of pulse density modulation for the control of the amplitude, frequency, and waveshape of the synthesized low-frequency signals. Adaptation of the proposed topology for power conversion to single-phase AC and DC voltage or current outputs is shown to be straightforward. The feasibility of the proposed power circuit and the control technique have been experimentally verified. >

106 citations


Journal ArticleDOI
TL;DR: Software considerations and test results are given for a topology processor that can track the changes in the network over time and it is expected that by knowing the changes from one cycle to the next, certain steps in thenetwork solution can be avoided or replaced with steps requiring significantly less computation.
Abstract: Software considerations and test results are given for a topology processor that can track the changes in the network over time. It is expected that by knowing the changes from one cycle to the next, certain steps in the network solution can be avoided or replaced with steps requiring significantly less computation. The steps of particular interest are the ordering and factoring of the network solution matrix. In the operator training simulator, where solution time is critical, the simulation computation slows down when changes take place in the network, but the presented topology processor may provide the means to keep up with real time. In the security analysis real-time time sequence, computation can be saved in the state estimator if its tracking topology processor is used. The use of this topology processor modifies the solution of the tracking mode. For large topology changes, it is the same as the conventional tracking mode. But for the more common small topology changes, the matrices are not rebuilt and considerable computation time is saved. >

101 citations


Proceedings ArticleDOI
01 Feb 1988
TL;DR: An experimental DC-to-DC converter prototype based on a zero-voltage switching, resonant circuit topology is described in this article, which is suitable for mounting directly on a circuit card.
Abstract: An experimental DC-to-DC converter prototype based on a zero-voltage switching, resonant circuit topology is described. The converter is suitable for mounting directly on a circuit card. The unit provides a regulated 5 V output at power levels up to 50 W with an input between 40 and 60 V. The switching frequency is between 20 and 24 MHz, depending on the input voltage and load. Differential input and output ripple and EMI are extremely low and somewhat difficult to measure. The converter prototype has been designed to demonstrate compatibility with a fully automated assembly process based on surface-mount technology. Solutions are presented to a number of problems, including MOSFET gate-drive and rectifier diode capacitance, that have seriously limited the performance of high-frequency converters operating with useful input and output voltages. >

85 citations


Journal ArticleDOI
TL;DR: It is shown that the basic topology and access scheme of Tree-Net can be extended so that a family of tree-structured fiber-optic MANs (metropolitan area networks) can be defined to suit different needs, including data, voice, and video integration.
Abstract: A fiber-optic architecture, Tree-Net, is introduced that does not require intermediate processing components and supports a large number of stations. Tree-Net is based on a tree topology, passive station taps, and implicit token protocol. The properties and performance of Tree-Net are evaluated. It is shown that the basic topology and access scheme of Tree-Net can be extended so that a family of tree-structured fiber-optic MANs (metropolitan area networks) can be defined to suit different needs, including data, voice, and video integration. >

64 citations


Journal ArticleDOI
TL;DR: An automatic understanding system using the techniques of image processing, pattern recognition, and artificial intelligence has been developed for electronic circuit diagrams to extract three categories of essential components: circuit symbols, characters, and connection lines.
Abstract: An automatic understanding system using the techniques of image processing, pattern recognition, and artificial intelligence has been developed for electronic circuit diagrams. Part of the system is presented to extract three categories of essential components: circuit symbols, characters, and connection lines. Each essential component consists of a set of picture segments which are appropriately detected by a segment tracking algorithm. A heuristic piecewise linear approximation algorithm is proposed to approximate picture segments for primitive recognition. On the basis of topological context, a one-pass manner called the relational best search method applies a depth first search technique uniting a set of specified rules during the traversal of a circuit diagram. This method combines the constituents of each circuit symbol or character into a cluster. All the clusters together with the remaining components are extracted and grouped into the three categories as soon as the traversal is finished. A variety of electronic circuit diagrams have been used for testing the component extractor. So far, the present extractor has shown favorable results.

53 citations


Journal ArticleDOI
TL;DR: In this paper, the waveforms of a square-wave DC-DC converter and a quasiresonant DCDC converter are examined in detail and a comparison is made between the switching losses and conduction losses for each topology.
Abstract: The waveforms of a square-wave DC-DC converter and a quasiresonant DC-DC converter are examined in detail and a comparison is made between the switching losses and conduction losses for each topology. Using data from commercially available semiconductor devices, conservative estimates are then given for the switching frequency at which the resonant approach becomes advantageous. The effect of an isolation transformer on this comparison is also addressed. >

50 citations


Journal ArticleDOI
TL;DR: Two forms of fast circuit switching are modeled and studied through mathematical analysis and Monte Carlo simulation, in which rather than first-come first-served the discipline is to search for a message whose destination queue is free.
Abstract: Two forms of fast circuit switching are modeled and studied through mathematical analysis and Monte Carlo simulation. The two examples described use the switching technique in an optical-fiber-based local area network with a star topology. The technique is compatible with time-division multiplexing techniques that are used for a range of traffic classes. Further, the technique trades transmission capacity for processing power, which is the critical limitation of the system. By means of a certain independence assumption, the first form of fast circuit switching is modeled as an M/G/1 queue. The results of the analysis show excellent agreement with simulation. The general result is that there is good system throughput, despite simplicity of processing. The second form, in which rather than first-come first-served the discipline is to search for a message whose destination queue is free, is studied by means of simulation alone. The results indicate an improved performance with a modest increase in processing power. >

33 citations



Proceedings ArticleDOI
A. Capel1, H. Spruyt, A. Weinberg, D. O'Sullivan, A. Crausaz, J.C. Marpinard 
11 Apr 1988
TL;DR: In this article, a lightweight and efficient converter topology is described that presents zero ripple current on both input and output terminals simultaneously, and static and dynamic analyses are performed by using state representation with the current-injected method.
Abstract: A lightweight and efficient converter topology is described that presents zero ripple current on both input and output terminals simultaneously. The static and dynamic analyses are performed by using state representation with the current-injected method. A hardware application suitable for a space-station battery conditioner is presented as a validation of the theoretical model. >

Journal ArticleDOI
TL;DR: A heuristic method is developed to assign links to a given topology so that the system reliability of the network is near optimal and the most reliable link should be assigned to the most vulnerable edge.
Abstract: The evaluation of the reliability of a given computer communication network is a NP-hard problem. Hence, the problem of assigning reliabilities to links of a fixed computer communication network topology to optimize the system reliability is also NP-hard. A heuristic method is developed to assign links to a given topology so that the system reliability of the network is near optimal. The method provides a way to assign reliability measures to the links of a network to increase overall reliability. It is based on the principle that the most reliable link should be assigned to the most vulnerable edge. The method computes an importance order for the edges of the network and uses the order to assign link reliabilities. If there are fewer than six links in a network, it can be shown that the method gives optimal assignment. >

Proceedings ArticleDOI
24 Oct 1988
TL;DR: In this paper, the main considerations in the design of a single-switch-per-phase converter for a switched reluctance motor (SRM) drive are described, with particular attention given to the choice of converter topology, the type of switching devices, the normalized rating of the power devices, and input filter design.
Abstract: The main considerations in the design of a single-switch-per-phase converter for a switched reluctance motor (SRM) drive are described, with particular attention given to the choice of converter topology, the type of switching devices, the normalized rating of the power devices, and input filter design. The converter uses MOSFET switches. Experimental verification is included with a 6/4 pole personal-computer-controlled prototype SRM drive. >

Journal ArticleDOI
W. McMurray1
01 Apr 1988
TL;DR: In this paper, a generalized concept of "sources" that embraces both power generators and power consumers is presented, which simplifies the basic topological aspects of power electronic converter circuits, which are reduced to an array of switches for selectively interconnecting two source systems.
Abstract: A generalized concept of 'sources' that embraces both power generators and power consumers is presented. This approach simplifies the basic topological aspects of power electronic converter circuits, which are reduced to an array of switches for selectively interconnecting two source systems. Capacitive and inductive filters can modify the nature of the systems, because they act as short-time sources and determine whether the converter sees a voltage source or a current source at its terminals. These differing source qualities require different types of switching devices and have ramifications in the mode of operation of the equipment. Some basic configurations are presented, and their significant properties are described, with emphasis on the most widely used circuits in high-power equipment, particularly AC/DC converters. >

Journal ArticleDOI
TL;DR: A novel architecture is described for point-to-multipoint distribution using coherent detection and a totally passive fiber bus to provide transmission at rates of a few hundred Mb/s without the need for a local oscillator at each station.
Abstract: A novel architecture is described for point-to-multipoint distribution using coherent detection and a totally passive fiber bus. Coherent technology is used initially to provide transmission at rates of a few hundred Mb/s without the need for a local oscillator at each station. It is expected that this architecture can then be expanded via WDM (wavelength-division multiplexing) to transport multiple wavelengths as coherent technology matures. The performance of the proposed topology is analyzed and compared to that of previous bus structures using variable and fixed taps with direct-detection receivers. This performance analysis consists essentially of a loss budget calculation intended to determine the relative numbers of stations which each of the architectures could support. Because the rates and loop lengths are modest and the spectral width of the sources associated with coherent communication are very small, dispersion (or rise-time budgeting) is not expected to present any real limitation for the systems considered here. A performance analysis and comparison of three tree structures is presented. Engineering issues and open questions are discussed. >

Journal ArticleDOI
TL;DR: It is shown how to generate a network topology that is optimized with respect to the communication patterns of a given task by an algorithm that takes as input a task graph and generates as output a topologies that closely matches the given input graph.
Abstract: The performance of a parallel algorithm depends in part on the interconnection topology of the target parallel system. An interconnection network is called reconfigurable if its topology can be changed between different algorithm executions. Since communication patterns vary from one parallel algorithm to another, a reconfigurable network can effectively support algorithms with different communication requirements. It is shown how to generate a network topology that is optimized with respect to the communication patterns of a given task. The algorithm presented takes as input a task graph and generates as output a topology that closely matches the given input graph. The topologies generated by the algorithm are analyzed with respect to optimum interconnection topologies for the best, worst, and average cases. Simulation results verify the average-case performance prediction and confirm that, on the average, the optimum topologies are generated. >

Proceedings ArticleDOI
05 Jun 1988
TL;DR: The authors propose the polymorphic torus, a regular mesh interconnection network in which each node is able to dynamically interconnect its ports, depending on its own data, to support nonlocal communication.
Abstract: A parallel algorithm is presented for labeling the connected components of multicolored digital images. The algorithm takes advantage of the bottom-up divide-and-conquer strategy applied in tree and pyramid architectures but only requires a mesh topology. To support nonlocal communication, where meshes perform poorly, the authors propose the polymorphic torus, a regular mesh interconnection network in which each node is able to dynamically interconnect its ports, depending on its own data. By having each node properly drive such an interconnection, communication links between processors get established and disconnected and, as a result, the effective network diameter is reduced. The proposed connected-component labeling algorithm requires O( square root n) steps for a square root n* square root n multicolored image of an n-processor polymorphic torus, which is the same performance achieved in a tree architecture with 2n-1 processors. The lower number of processors and the simpler topology of polymorphic torus (vs. tree) make it a very suitable approach to mesh augmentation for intermediate-level vision applications. >


Journal ArticleDOI
TL;DR: In this article, a general and efficient method for transient simulation of HVDC converters is presented, which utilizes a novel algorithm that is based on network topological concepts and provides an efficient solution to the problem of modeling the inherently nonlinear characteristics and time-varying topology of static power converters caused by the switching action of the thyristor valves.
Abstract: A general and efficient method is presented for transient simulation of HVDC converters. The method utilizes a novel algorithm that is based on network topological concepts and provides an efficient solution to the problem of modeling the inherently nonlinear characteristics and time-varying topology of static power converters caused by the switching action of the thyristor valves. The application of the algorithm to a six-pulse converter unit results in an extremely flexible and efficient model that can be easily interfaced to both the AC and DC sides of an integrated AC/DC system. >


Proceedings ArticleDOI
C. Guo1, Edouard Ngoya1, Raymond Quéré1, Marc Camiade, J. Obregon1 
25 May 1988
TL;DR: In this article, a method for deriving the optimal operating conditions of a given MESFET needed to obtain an optimal frequency multiplier has been proposed, where no topology of the embedding network is to be chosen a priori.
Abstract: A method is proposed for deriving the optimal operating conditions of a given MESFET needed to obtain an optimal frequency multiplier. The key point of this approach is that no topology of the embedding network is to be chosen a priori. The optimum bias voltages and the optimum load impedances (including possible feedback circuit) are found. The method has been applied to design doublers at low frequencies from 10-20 GHz and at millimeter-wave frequencies from 20-40 GHz. Although the experimental doublers are still under measurement, first results have given good agreement with theoretical predictions. >

Book ChapterDOI
TL;DR: In this paper, the authors survey what is known about geodetic graphs of diameter two and discuss the implications of a new strong necessary condition for the existence of such a graph.
Abstract: We survey what is known on geodetic graphs of diameter two and discuss the implications of a new strong necessary condition for the existence of such graphs.

01 Jun 1988
TL;DR: A new scheme for fast control of 3-stage Benes networks is introduced and studied, and several problems are shown to fit the new scheme, namely, biontic sorting, FFT, tree algorithms and matrix computations.
Abstract: Regular rectangular multistage interconnection networks that are complete and have the single path property are increasingly important in large parallel computing systems. The efficiency of such networks is critical to the overall system performance, and it depends on the structure, functional capabilities and routing control of the network. Much of the previous research has focused on specific networks. The objective of this dissertation is to study and characterize an important class of such networks. In particular, the relationships between network functionality and topology, switch size, control and modularity. The one-to-one correspondence between topology and functionality is shown, necessary and sufficient topological conditions for a network to realize all the permutations of another network are established, and optimal algorithms to decide if a network realizes all the permutations of another are developed. The single path property makes control via control tags potentially efficient. Two different control schemes are introduced where the control tags are the same as, or a function of, destination tags. The structure of these "easy-to-control" networks is shown to be recursive. Based on this recursiveness, the networks of several interesting network subclasses are shown to be functionally equivalent, namely, the subclass of doubly controllable networks, that is, easy-to-control from left to right and from right to left, the subclass of modular networks where all the stages are identical, and the subclass of r-ary networks, where the stages permute and transform $r$-ary digits. These single path networks do not realize all permutations. Multiple path Benes networks do but are a slow-to-control alternative. Accordingly, a new scheme for fast control of 3-stage Benes networks is introduced and studied, and several problems are shown to fit the new scheme, namely, biontic sorting, FFT, tree algorithms and matrix computations. Also, the random walk computation is parallelized and shown to fit this control scheme.

Journal ArticleDOI
TL;DR: A model by Kohonen is extended to allow the application of topology-conserving maps to the control of "ballistic" movements of a robot arm and it is shown that it greatly enhances the efficiency of the learning algorithm used, compared to the case were the units learn their linear mappings independently.

Journal ArticleDOI
TL;DR: In this article, the necessary and sufficient topological conditions under which one can transfer all independent sources of a no-gain nonlinear resistive network to the branches with positive linear resistors are derived.
Abstract: The necessary and sufficient topological conditions under which one can transfer all independent sources of a no-gain nonlinear resistive network to the branches with positive linear resistors are derived. Such a relocation of sources allows an estimate, practically without computation, of the greatest possible voltage and current in the circuit. The main theorem proved here shows that the simple localization of the solutions can, practically without computation, be made for a very large class of nonlinear circuits. >

Proceedings ArticleDOI
25 May 1988
TL;DR: In this article, the authors show that added power and third-order intermodulation can be approximated with a symmetrical source and load-pull single-tone measurement setup coupled with optimization software.
Abstract: Using the narrow-bandwidth approximation, the authors show that added power and third-order intermodulation can be approximated with a symmetrical source and load-pull single-tone measurement setup coupled with optimization software. This measurement setup has a completely symmetrical topology allowing simultaneous active source and load-pull. The device under test is loaded by 50 Omega at the harmonic frequencies. A rigorous calibration procedure was implemented and validated at low power levels by comparison with an HP 8510 network analyzer. The data acquisition software is described, and large-signal experimental results are given for a typical transistor. >

Proceedings ArticleDOI
K. Schwan1, W. Bo1
01 Jan 1988
TL;DR: Communication topologies are currently implemented as an extension of the Intel iPSC hypercube's operating system kernel and are used with several applications programs, including a large finite element analysis program used for metalforming applications (termed ALPID).
Abstract: The programming of a large-scale multicomputer that exhibits an interconnection structure known to the applications programmer (e.g. a hypercube or mesh) requires the explicit construction and use of complex communication structures for connecting the application's parallel tasks. Such structures are used for a wide variety of functions, including the exchange of data or control information relevant to the tasks' computations and/or communications required for task synchronization, message forwarding/filtering under program control, and others. Topologies is an operating system construct with which programmers may efficiently implement arbitrary communication graphs linking multiple tasks of a parallel program. In addition, with each topology may be associated user-defined services, which may perform computations for communications traversing the topology. For example, application-dependent services may compute global sums or minima for values being communicated among the tasks linked by a topology, and the operating system or programmer may use a topology's concatenation service in the implementation of monitoring, file storage, or virtual terminal services.Communication topologies are currently implemented as an extension of the Intel iPSC hypercube's operating system kernel and are used with several applications programs, including a large finite element analysis program used for metalforming applications (termed ALPID). Future extensions concern the restructuring of the operating system kernel to support services of different 'weights' and hardware support for the efficient execution of selected services in conjunction with message routing.

Proceedings ArticleDOI
11 Apr 1988
TL;DR: In this paper, a four-level computer modeling is proposed for computer-aided design and analysis (CADA) of DC-machine topology on SPICE2 to meet different simulation requirements, including magnetic saturation, armature reaction phenomena, current dependence of winding circuit parameters, and eddy current effects.
Abstract: Four-level computer modeling is proposed for computer-aided design and analysis (CADA) of DC-machine topology on SPICE2 to meet different simulation requirements. The models account for the magnetic saturation, armature reaction phenomena, current dependence of winding circuit parameters, and eddy current effects. The approach enables designers to simulate the static and dynamic characteristics of the whole converter drive system, including a DC machine driven more simply, practically, and reliably in one simulation run. Some simulations that demonstrate the benefits of the approach are presented. >

Journal ArticleDOI
TL;DR: A novel approach for simulating communication networks is discussed and illustrated with two examples of a token-passing network based on a graphical representation of the network consisting of three components: topology, nodes, and protocols.
Abstract: A novel approach for simulating communication networks is discussed and illustrated with two examples of a token-passing network. The method is based on a graphical representation of the network consisting of three components: topology, nodes, and protocols. The topology and nodes are drawn to a network specification. The protocols are drawn by using Petri nets with some extended features. A simulation model can be automatically generated from this representation. Results of the simulation are compared to those of an analytical model, showing excellent agreement. >

Journal ArticleDOI
01 Sep 1988
TL;DR: A compact model of the Power VDMOS Transistor compatible with the circuit simulator `` SPICE2'' is described in this article and this model is applied to the simulation of switching circuit with resistive and inductive loads.
Abstract: A compact model of the Power VDMOS Transistor compatible with the circuit simulator `` SPICE2'' is described in this article. This model is applied to the simulation of switching circuit with resistive and inductive loads; comparisons with experimental results are presented.