Showing papers on "Topology (electrical circuits) published in 1989"

The Cascade-Correlation Learning Architecture

Abstract: Cascade-Correlation is a new architecture and supervised learning algorithm for artificial neural networks. Instead of just adjusting the weights in a network of fixed topology. Cascade-Correlation begins with a minimal network, then automatically trains and adds new hidden units one by one, creating a multi-layer structure. Once a new hidden unit has been added to the network, its input-side weights are frozen. This unit then becomes a permanent feature-detector in the network, available for producing outputs or for creating other, more complex feature detectors. The Cascade-Correlation architecture has several advantages over existing algorithms: it learns very quickly, the network determines its own size and topology, it retains the structures it has built even if the training set changes, and it requires no back-propagation of error signals through the connections of the network.

The resonant DC link converter-a new concept in static power conversion

Abstract: A novel approach to realizing efficient high-performance power converters is presented. The concept of a resonant DC link inverter has been proposed and realized with the addition of only one small inductor and capacitor to a conventional voltage source inverter circuit. The proposed technology is capable of switching almost an order of magnitude faster than state-of-the-art voltage source inverters at significantly improved efficiencies using the same family of devices. The topology is especially suitable for high-power applications using gate turn-off devices. A 4.5 kW inverter has been fabricated and tested extensively in the laboratory, and the superior characteristics of the resonant DC link topology have been verified. >

Zero-switching-loss inverters for high-power applications

Abstract: The development of zero switching loss inverters has attracted much interest for industrial applications. Two topologies for realizing zero switching losses in high-power converters are proposed. The actively clamped resonant DC link inverter uses the concept of a lossless active clamp to restrict voltage stresses to only 1.3-1.5 supply voltage. For applications demanding substantially better spectral performance, the resonant pole inverter (RPI), also called the quasi-resonant current mode inverter, is proposed as a viable topology. Using only six devices rated at supply voltage, this circuit transfers the resonant components to the AC side of each phase and thus requires additional inductor and capacitor (LC) components. On the other hand, the RPI is capable of true pulsewidth modulation (PWM) operation at high frequency as opposed to discrete pulse modulation operation found in resonant DC link invertors. >

A survey of modern high-performance switching techniques

Abstract: A survey of high-performance switch fabric architectures which incorporate fast packet switching as their underlying switching technique to handle various traffic types is presented. A descriptive overview of the major activities in this rapidly evolving field of telecommunications is given. The switch fabrics are classified into the following categories: banyan and buffered banyan-based fabrics, sort-banyan-based fabrics fabrics with disjoint-path topology and output queuing, crossbar-based fabrics, time division fabrics with common packet memory, and fabrics with shared medium. >

A noise-shaping coder topology for 15+ bit converters

Abstract: A topology for high-precision noise-shaping converters that can be integrated on a standard digital IC process is presented. This topology uses a multibit noise-shaping coder and a novel form of dynamic element matching to achieve high accuracy and long-term stability without requiring precision matching of components. A fourth-order noise-shaping D/A (digital-to-analog) conversion system using a 3-b quantizer and a dynamic element-matching internal D/A converter, fabricated in a standard double-metal 3- mu m CMOS process, achieved 16-bit dynamic range and a harmonic distortion below -90 dB. This multibit noise-shaping D/A conversion system achieved performance comparable to that of a 1-bit noise-shaping D/A conversion system that operated at nearly four times its clock rate. >

ISAAC: a symbolic simulator for analog integrated circuits

Abstract: The symbolic simulator ISAAC (interactive symbolic analysis of analog circuits) is presented. The program derives all AC characteristics for any analog integrated circuit (time-continuous and switched-capacitor, CMOS, JFET, and bipolar) as symbolic expressions in the circuit parameters. This yields analytic formulas for transfer functions, CMRR (common-mode rejection ratio), PSRR (power-supply rejection ratio), impedances, noise, etc. Two novel features are included in the program. First, the expressions can be simplified with a heuristic criterion based on the magnitudes of the elements. This yields interpretable formulas showing only the dominant terms. Second, the explicit representation of mismatch terms allows the accurate calculation of second-order effects, such as the PSRR. ISAAC provides analog designers with more insight into the circuit behavior than do numerical simulators and is a useful tool for instruction or designer assistance. Moreover, it generates complete analytic AC circuit models, which are used for automatic sizing in a nonfixed topology analog module generator. The program's capabilities are illustrated with several examples. The efficiency is established by a dedicated sparse-matrix algorithm. >

Analog circuit design optimization based on symbolic simulation and simulated annealing

Abstract: A methodology for the automatic design optimization of analog integrated circuits is presented. A non-fixed-topology approach is realized by combining the optimization program OPTIMAN with the symbolic simulator ISAAC. After selecting a circuit topology, the user invokes ISAAC to model the circuit. ISAAC generates both exact and simplified analytic expressions, describing the circuit's behavior. The model is then passed to the design optimization program OPTIMAN. This program is based on a generalized formulation of the analog design problem. For the selected topology, the independent design variables are automatically extracted and OPTIMAN sizes all elements to satisfy the performance constraints, thereby optimizing a user-defined design objective. The global optimization method used on the analytic circuit models is simulated annealing. Practical examples show that OPTIMAN quickly designs analog circuits, closely meeting the specifications, and that it is a flexible and reliable design and exploration tool. >

Buck quasi-resonant converter operating at constant frequency: analysis, design and experimentation

Abstract: A buck pulsewidth modulated zero-current switching quasi-resonant converter (buck PWM ZCS QRC) operating at constant frequency is discussed. Operating principle and design-oriented analysis are presented with normalized design curves, design procedure, design example, simulations, and experimental results. The new topology, which can be considered as a particular one, is compared with the well-established buck frequency-modulated zero-current switching quasi-resonant converter (buck FM ZCS QRC) proposed by Fred C. Lee (1988). >

Dc/dc converter switching at zero voltage

Abstract: A two switch, DC/DC converter provides sufficient inductive energy storage at the termination of the "on" period of each switch to alter the charge on the intrinsic and stray capacitance of the combination of switches producing zero voltage across the alternate switch prior to its turn on. A short dead-band between the turn on pulses provided by the control circuit allows time for this transition. Thus the energy stored in the capacitance of the switches is returned to the source and load rather than being dissipated in the switching devices. This greatly improves the efficiency of the converter particularly when operating at high frequency. The unique topology of the converter provides other new and useful characteristics in addition to zero voltage switching capability such as operation as constant frequency with pulse-width-modulation for regulation, quasi-square wave output current, and the ability to integrate the magnetic elements with or without coupling.

Topology design and bandwidth allocation in ATM nets

Abstract: The design of a P/S network embedded into a backbone facility network is discussed. The problem is formulated as a network optimization problem where a congestion measure based on the average packet delay is minimized, subject to capacity constraints posed by the underlying facility trunks. The variables in this problem are the routing on the express pipes (i.e. the channels that interconnect the P/S modes) and the allocation of bandwidth to such pipes. An efficient algorithm is presented for the solution of the above problem and it is applied to some representative examples. It is shown that for some test cases the congestion measure is substantially reduced with respect to the values obtained when the embedded topology is kept identical to the backbone topology. Dynamic reconfiguration schemes where the embedded topology is periodically adjusted to track the fluctuations in traffic requirements are discussed. >

Parallel resonant DC link circuit-a novel zero switching loss topology with minimum voltage stresses

Abstract: A parallel-resonant DC link (PRDCL) circuit topology is presented as a way to realizing zero-switching-loss, DC-AC high switching frequency power conversion. The circuit is used as an interface between DC voltage supply and the voltage-source PWM (pulse-width-modulated) inverter. It provides a short zero-voltage period in the DC link of the inverter to allow zero-voltage switching to take place in the PWM inverter. The peak voltage stress on the PWM inverter switches is limited to the DC supply voltage. Another significant advantage of the proposed circuit is that the inverter can be controlled by the conventional PWM strategy. The circuit is systematically analyzed, and its operation principle is explained in detail. Design considerations and formulae are also presented. A complete zero-voltage-switching DC-AC converter system consisting of the proposed circuit and the PWM inverter is simulated on computer. >

Method and system for automatically visually inspecting an article

Abstract: A method and system are disclosed for automatically visually inspecting an article such as an electronic circuit wherein both reference and non-reference algorithms are utilized to detect circuit defects. The system includes a pipelined cellular image processor which is utilized to implement the non-reference algorithm and an arithmetic logic unit (ALU) is coupled to the output of the cellular image processor to perform the reference method. The non-reference method includes a spaces and traces algorithm and the reference method includes a topology matching algorithm. The system also includes an algorithm for locating and gauging critical areas of the circuit with sub-pixel accuracy. The cellular image processor is supported by a matched host image processor system

A new topology for single phase UPS systems

Abstract: A power converter topology suitable for online single-phase uninterruptible power supply (UPS) systems is presented. The converter uses only four switches, five if a low-voltage battery and resonant link operation are required, to realize very desirable features. These include independent control of the input and output currents a common neutral connection, line conditioning, sinusoidal input currents independent of load current, and battery charge/discharge regulation. Detailed simulation results and experimental results are included. >

Using the multistage cube network topology in parallel supercomputers

Abstract: A critical component of any large-scale parallel processing system is the interconnection network that provides a means for communication along the system's processors and memories. Attributes of the multistage cube topology that have made it an effective basis for interconnection networks and the subject of much ongoing research are reviewed. These attributes include O(N log/sub 2/N) cost for an N-input/output network, decentralized control, a variety of implementation options, good data-permuting capability to support single-instruction-stream/multiple-data-stream (SIMD) parallelism, good throughput to support multiple-instruction-stream/multiple-data-stream (MIMD) parallelism, and ability to be partitioned into independent subnetworks to support reconfigurable systems. Examples of existing systems that use multistage cube networks are considered. The multistage cube topology can be converted into a single-stage network by associating with each switch in the network a processor (and a memory). Properties of systems that use the multistage cube network in this way are examined. >

Analysis and design of a low-cost converter for switched reluctance motor drives

Abstract: The analysis and design of a low-cost, one-switch-per-phase converter topology suitable for low-performance applications in switched reluctance motor (SRM) drives is presented. The converter has the advantage of a minimum possible number of semiconductor devices in the power circuit without the attendant need for a bifilar winding. Consequently, its drive requirements are minimal and the windings are simple. This is achieved through the elimination of the additional semiconductor switch(es) normally required for regeneration. Energy stored in the phase windings during conduction time is partially dissipated in a resistor, while the rest is converted to mechanical power. A complete steady-state analysis of the drive is given, including the input filter parameters. Closed-form expressions for determining the current and voltage stresses on the semiconducting devices are derived and cast in normalized form for use in selecting the ratings of the power devices. Experimental verification of the key results is provided from a 6/4 pole SRM drive system. >

A 10-bit video BiCMOS track-and-hold amplifier

Abstract: A 1.2- mu m VLSI BiCMOS technology has been used to implement a monolithic video track-and-hold amplifier that settles to an accuracy of 10 b in 15 ns. This level of performance is competitive with hybrid track-and-hold circuits and surpasses previously reported monolithic implementations by nearly two orders of magnitude. The amplifier's design is based on a closed-loop topology incorporating two BiCMOS folded-cascode gain stages, an NMOS sampling switch, and a BiCMOS switch driver with 1-ns transitions between +or-4 V. The circuit operates from +or-5-V power supplies and is capable of driving a 50- Omega load with +or-1-V swings. For a fully differential implementation, the power dissipation is 1.2 W. The amplifier can be integrated either as a stand-alone track-and-hold circuit or as the front end of an analog-to-digital conversion system for video and high-speed instrumentation applications. >

Steady state analysis of the parallel resonant converter with LLCC-type commutation network

Abstract: A novel converter topology known as LLCC-type parallel resonant converter (PRC-LLCC), in which the tank circuit consists of two inductors and two capacitors, is introduced. Using the state-plane approach, the steady-state analysis of the PRC-LLCC operating in the continuous conduction model is carried out. It is shown that by using the state variable transformation technique the steady-state response of the converter can be represented by two state-plane diagrams. Using these diagrams and the circuit equations, a set of control characteristic curves which are useful for converter design is derived. Based on these curves, a design procedure along with a specific design example is given. The correctness of the analysis results is verified via computer simulations. >

A new zero voltage and zero current power-switching technique

Abstract: An outline is presented of work done by the authors on a novel converter topology where the power switching occurs at both zero current and zero voltage, giving it some major advantage over the present state of the art. A description is given of the application of this topology to both high and low-output-voltage converters. Design details and test results are given, together with a full analysis of the operation of the converters. >

Event driven topology broadcast without sequence numbers

Abstract: An algorithm is presented that allows each node in a computer network to maintain a correct view of the network topology despite link and node failures. Reliability is achieved without transmitting any information other than the operational status of links. Messages are only sent in response to topological changes: periodic retransmission is not required. >

Synthesis of PWM and quasi-resonant DC-to-DC power converters

Abstract: Synthesis of DC-to-DC converter topologies in the two largest families - PWM and Quasi-Resonant (QR) - is completed in this thesis In a PWM converter, two linear time-invariant networks, consisting of only capacitors and inductors, source and load, are switched at constant frequency with duty ratio D. From defining assumptions, several general properties of PWM converter networks are derived. The established general properties interrelate the number of elements, attainable DC conversion ratio M(D), and features such as continuous terminal currents or possible coupling of inductors. Based on matrix representation of the converter topology, the systematic synthesis procedure for generation of PWM converters with a given number of reactive elements is constructed. A prescribed set of requirements is the input for the procedure. The requirements may include desired DC conversion ratio, continuous terminal currents, possible coupling of inductors and a given number of switches. In particular, the number of switches implemented as transistors can be specified. Outputs of the procedure are complete classes of PWM converters that satisfy the input requirements. A number of useful PWM topologies, which have not been identified before, are uncovered. A comparison of members of the classes is included. Several extensions of PWM converters are considered, including insertion of the isolation transformer and two discontinuous operating modes for which unified DC analyses are completed. Quasi-Resonant converters are defined as two-switch PWM converter networks to which resonant elements are added. Synthesis of QR, converters is based on the recognition that there are only a finite number of topologically distinct positions for resonant elements within a two-switch PWM parent converter. If a single resonant inductor and a single resonant capacitor are added to a two-switch PWM topology, examination of all possible positions yields a total of six QR classes, which come in dual pairs. Two pairs are identified as known QR classes, namely, Zero-Current/Zero-Voltage (ZV/ZC) and Zero-Current/Zero-Voltage Quasi-Square-Wave (ZC-QSW/ZV-QSW). The remaining two classes, named Off-Resonant and On-Resonant Quasi-PWM (Q[f]-PWM/Q[n]-PWM), have not been recognized so far. The names originate from the fact that Q-PWM converters can be regarded as PWM converters operating in both discontinuous modes simultaneously. The synthesis procedure can be generalized to encompass additional resonant elements. As an example, classes of Zero-Current and Zero-Voltage Multi-Resonant (ZC-MR/ZV-MR) converters are formally defined. In contrast to square-wave switch waveforms in PWM converters, all QR topologies exhibit smooth quasi-sinusoidal waveforms and therefore reduced switching losses. Of particular interest are operating modes in which all switching transitions are at zero current or at zero voltage. A study of operating modes and a DC analysis unified with respect to all PWM parents and all topological variations are carried out for four selected classes of QR Converters - Q[n]-PWM, ZV, ZV-QSW, and ZV-MR. It is emphasized that for a QR converter, topology alone is not sufficient to derive DC conversion properties. Subject to different switch implementations and control timing, the emerging operating modes can result in vastly different behavior of the same converter topology. Two switch implementations are considered - conventional, with one controllable switch and one diode, and the one that resembles the technique of synchronous rectification - with two controllable switches. In the first case, with the exception of converters in two Q-PWM classes, only variable-frequency control is applicable. However, if both switches are controllable, constant-frequency control is restored in all QR classes, and several novel operating modes of practical interest are uncovered. Various QR classes and operating modes are compared with respect to sets of switching transitions, sensitivity to parasitic elements, available operating region, frequency range and stresses on switching devices. The role of free parameters in various design trade-offs is exposed, thus allowing a designer to select and realize the topology best suited for a particular application.

Evaluation and design of megahertz-frequency off-line zero-current-switched quasi-resonant converters

Abstract: A performance comparison of flyback, forward, and half-bridge zero-current-switched quasi-resonant converter topologies for high-frequency offline applications is presented. It is shown that the half-bridge topology with secondary side resonance operating in half-wave mode is most suitable. A complete design procedure for the half-bridge power stage and the voltage-feedback control is presented together with experimental results for a 300 V DC hybridized converter which operates with conversion frequencies from 400 kHz to 2 MHz and delivers 1.5-16 A at 5 V DC. >

Augumented multiprocessor networks

Abstract: An augmented De Bruijn multiprocessor network. Multiple microprocessors having a constant number of I/O ports are connected according to a network technique which yields a machine of predetermined degree. A modified binary De Bruijn graph of degree four, DG(2,k), is used as the basis for the preferred implementation. An augmentation technique supplements the basic De Bruijn topology with a 2D-mesh in a first set of steps and with a 3D-mesh in a second set of steps. The resulting machine topology contains substantially all of the problem-solving techniques important in multiprocessing, while maintaining a machine of constant degree.

Accurate current conveyor integrated circuit

Abstract: An integrated circuit implementation of a novel current conveyor topology is described. The IC offers significantly improved performance in the areas of accuracy, frequency bandwidth, transient response, output impedance and distortion due to an innovative connection of Wilson current mirrors and fabrication on a complementary npn-pnp bipolar process.

A general-purpose computer program for the Volterra-series analysis of nonlinear microwave circuits

Abstract: A computer program is described that performs a Volterra-series analysis of a weakly nonlinear microwave circuit having an arbitrary topology. The program uses the method of nonlinear currents and a nodal formulation. In this approach, each nonlinear circuit element is described as a linear element in parallel with a set of current sources; each current source represents a single order (greater than one) of the mixing products, and its current is a nonlinear function of the node-voltage components at lower-order mixing frequencies. The weakly nonlinear circuit is reduced to a linear circuit, which contains the linear elements and the linear parts of the nonlinear elements, and a set of excitation sources. The program is intended primarily for use in the design of microwave circuits; its catalog of circuit elements includes the distributed elements necessary for such work. Because the program formulates and solves the circuit equations numerically, the user need not simplify either the circuit or the model of the solid-state device, or make any of the other common simplifying assumptions. >

Topological properties of Manhattan street networks

Abstract: The Manhattan street network (MSN) is a two-connected regular mesh network (RMN) with unidirectional communication links. The letter is concerned with the determination of the minimum mean internode distances (MIMINDs) and the topology z-transforms, T(z), of two different types of MSN.

Active power filters using resonant pole inverters

Abstract: The use of a new soft switching inverter topology, the resonant pole inverter (RPI), for harmonic compensator realization, is proposed. Using resonant transitions to minimize switching losses, the topology is suitable for use with GTOs and other gate turn-off devices. Switching frequencies on the order of 10-20 kHz at multikilowatt power levels are feasible. A current-mode modulation strategy is proposed and is seen to realize good spectral characteristics. Extensive simulation and experimental results of a 10 kVA GTO resonant pole inverter switching between 10 and 20 kHz confirm the validity of the approach. >

A high-density modular power processor for distributed military power systems

Abstract: A high-density power processor in a SEM (standard electronic module) Format-E package is described. The power converter features a full-bridge PWM (pulse-width modulated) topology that uses transition resonance to achieve zero-voltage switching. The switching sequence of the phase-shifted topology simplifies the MOSFET drive circuitry. The converter's tolerance to low magnetizing inductance reduces the volume required for the power transformer. A low-bandwidth control loop regulates the output currents of parallel units, providing excellent DC load-sharing characteristics while allowing each unit to respond to dynamic loads with its own high-bandwidth loop. The parallel modules are self-synchronizing in frequency and can be synchronized to an external clock. A high-density packaging approach is used. >

A fast integer algorithm for observability analysis using network topology

Abstract: An integer algorithm for determining the observability of a power system network with its linearized state estimator model is presented. By using some properties of the allocation of the flow and injection measurements and the network topology, the algorithm manipulations only integer numbers in the measurement Jacobian matrix. Theorems that determine the rank of the special kinds of matrices are proposed to speed up the observability analysis. Neither manipulation of real numbers nor a complicated combinatorial problem is involved in the proposed algorithm. Therefore, it is much simpler and the speed for observability analysis is much faster compared to previous methods. Moreover, no numerical problems are encountered. A detailed example of the IEEE 14-bus test system following the steps in the algorithm is presented and test results on the algorithm are reported. >

On the convergence of block relaxation methods for circuit simulation

Abstract: The authors developed sufficient conditions for the convergence of several block relaxation methods. They first consider time-point relaxation methods, namely the block Gauss-Seidel-Newton (G-S-N) and the block Newton-Gauss-Seidel (N-G-S) algorithms. The previously known sufficient condition for convergence of the G-S-N and the N-G-S algorithms requires: (1) a capacitor connected between every node in the circuit and the reference ground node: and (2) the choice of a sufficiently small time step for the implicit integration formula used to discretize (in time) the circuit equations. The authors derive a sufficient condition that is less restrictive than (1) above. For a given partitioning of a circuit, they define a set (possibly empty) of feedback nodes that capture the topology of the partitioned circuit to a certain extent. They then show that the G-S-N and the N-G-S algorithms converge. >