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Showing papers on "Topology (electrical circuits) published in 1992"


Proceedings ArticleDOI
29 Jun 1992
TL;DR: In this paper, a multilevel commutation cell is introduced for high-voltage power conversion, which can be applied to either choppers or voltage-source inverters and generalized to any number of switches.
Abstract: The authors discuss high-voltage power conversion. Conventional series connection and three-level voltage source inverter techniques are reviewed and compared. A novel versatile multilevel commutation cell is introduced: it is shown that this topology is safer and more simple to control, and delivers purer output waveforms. The authors show how this technique can be applied to either choppers or voltage-source inverters and generalized to any number of switches. >

1,197 citations


Journal ArticleDOI
30 Aug 1992
TL;DR: Experiments indicate that the performance of the Kohonen projection method is comparable or better than Sammon's method for the purpose of classifying clustered data.
Abstract: A nonlinear projection method is presented to visualize high-dimensional data as a 2D image. The proposed method is based on the topology preserving mapping algorithm of Kohonen. The topology preserving mapping algorithm is used to train a 2D network structure. Then the interpoint distances in the feature space between the units in the network are graphically displayed to show the underlying structure of the data. Furthermore, we present and discuss a new method to quantify how well a topology preserving mapping algorithm maps the high-dimensional input data onto the network structure. This is used to compare our projection method with a well-known method of Sammon (1969). Experiments indicate that the performance of the Kohonen projection method is comparable or better than Sammon's method for the purpose of classifying clustered data. Its time-complexity only depends on the resolution of the output image, and not on the size of the dataset. A disadvantage, however, is the large amount of CPU time required. >

253 citations


Proceedings ArticleDOI
23 Feb 1992
TL;DR: In this paper, a novel active harmonic-neutralizing filter is proposed which eliminates current harmonic effects, caused by any configuration of nonlinear loads in a three-phase, four-wire systems.
Abstract: A novel active harmonic-neutralizing filter is proposed which eliminates current harmonic effects, caused by any configuration of nonlinear loads in a three-phase, four-wire systems. The authors present proposed filter topologies and simulation results verifying the concept. Theoretical analysis of the circuit is included to facilitate a detailed converter design. The proposed topology is shown to have distinct advantages over traditional approaches to the problem, particularly over the three single-phase inverter approach. >

215 citations


Journal ArticleDOI
TL;DR: The development of a high-Q approximation, which simplifies the design procedure is presented, and the closed-loop class E circuit shows great promise, especially for circuits with unusually low coefficients of coupling.
Abstract: The use of a multifrequency transmitter coil driver based on the class E topology is described. The development of a high-Q approximation, which simplifies the design procedure is presented. A closed-loop controller to compensate for transmitter and receiver variations, and a method of data modulation using synchronous frequency shifting are described. The closed-loop class E circuit shows great promise, especially for circuits with unusually low coefficients of coupling. Currents of several amperes, at radio frequencies, can easily and efficiently be obtained. >

213 citations


Journal ArticleDOI
TL;DR: A computer-oriented method for the time-domain analysis of networks with internally controlled ideal switches is presented, and it is shown that Dirac impulses must be considered for the analysis of some switched networks.
Abstract: A computer-oriented method for the time-domain analysis of networks with internally controlled ideal switches is presented No assumptions are made about the continuity of the circuit response at the switching instants; even Dirac impulses are permitted In fact, it is shown that Dirac impulses must be considered for the analysis of some switched networks, even though they may only be present for intermediate steps of the analysis Several topological changes may be needed at each switching instant to ensure that the topology after switching is valid The theories have been implemented in a computer program, SWANN The network equations are generated with a two-graph modified nodal analysis technique, rather than the state equation formulation Various internally controlled switches are permitted, such as the ideal diode, thyristor, and voltage- and current-controlled switches Numerical results show the generality and accuracy of the method on three switched networks >

192 citations


Journal ArticleDOI
TL;DR: This work presents an efficient implementation of vector clocks that reduces the size of timestamp related information to be transferred in a message and is resilient to changes in the topology of the distributed system.

177 citations


Journal ArticleDOI
TL;DR: The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently.
Abstract: Due to the variety of architectures that need be considered while attempting solutions to various problems using neural networks, the implementation of a neural network with programmable topology and programmable weights has been undertaken. A new circuit block, the distributed neuron-synapse, has been used to implement a 1024 synapse reconfigurable network on a VLSI chip. In order to evaluate the performance of the VLSI chip, a complete test setup consisting of hardware for configuring the chip, programming the synaptic weights, presenting analog input vectors to the chip, and recording the outputs of the chip, has been built. Following the performance verification of each circuit block on the chip, various sample problems were solved. In each of the problems the synaptic weights were determined by training the neural network using a gradient-based learning algorithm which is incorporated in the experimental test setup. The results of this work indicate that reconfigurable neural networks built using distributed neuron synapses can be used to solve various problems efficiently. >

176 citations


Journal ArticleDOI
TL;DR: An analog circuit structure for the realization of discrete-time cellular neural networks (DTCNNs) is introduced by a balanced clocked circuit based on the idea of conductance multipliers and operational transconductance amplifiers.
Abstract: An analog circuit structure for the realization of discrete-time cellular neural networks (DTCNNs) is introduced. The computation is done by a balanced clocked circuit based on the idea of conductance multipliers and operational transconductance amplifiers. The circuit is proposed for a one-neighborhood on a hexagonal grid, but can also be modified to larger neighborhoods and/or other grid topologies. A layout was designed for a standard CMOS process, and the corresponding HSPICE simulation results are given. A test chip containing 16 cells was fabricated, and measurements of the transfer characteristics are provided. The functional behavior is demonstrated for a simple example. >

132 citations


Journal ArticleDOI
TL;DR: In this article, the fundamental power processing properties of switching converter circuits are modeled using generalized power-conservative (POPI) networks, and the application of the gyrator to network two voltage sources and the use of the loss-free resistor as a unity power factor rectifier are described.
Abstract: The fundamental power-processing properties of switching converter circuits are modeled using generalized power-conservative (POPI) networks. Depending on the application, it may be most appropriate to model the first-order converter properties as those of an ideal transformer, gyrator, loss-free resistor, or other POPI network. These basic functions can be obtained either through selection of a topology that naturally possesses the desired characteristics or by addition of a suitable control network. Some well-known converter topologies are shown to behave naturally as gyrators, loss-free resistors, and constant power networks. The application of the gyrator to network two voltage sources and the use of the loss-free resistor as a unity power factor rectifier are described. >

131 citations


Proceedings ArticleDOI
23 Feb 1992
TL;DR: In this paper, the buck and boost topology was employed for the zero-voltage-switching (ZVS) bidirectional converter for the NASA EOS (Earth Observing System) satellite.
Abstract: The design of a pulse-width-modulated (PWM) zero-voltage-switching (ZVS) bidirectional converter is presented. The bidirectional converter employs a buck and boost topology using FET devices for both switches. ZVS is obtained by selecting the power stage inductance so that the switches always turn on when the MOSFET body diode is conducting. A four-module, multiphase topology is employed to significantly reduce the input and output ripple current. Besides obtaining high efficiency and light weight, the converter is also shown to possess excellent small-signal characteristics. It is applied to the design of the battery charger/discharger for the NASA EOS (Earth Observing System) satellite. Both theoretical and experimental results are presented. >

123 citations


Proceedings ArticleDOI
29 Jun 1992
TL;DR: In this article, a switched capacitor DC-DC power converter topology consisting of n stages of semiconductor switches and capacitors is described, where switches connect the capacitors across the input source during the charging phase and then across the load during the discharge phase to step down the input voltage by a nominal ratio n further control of the output voltage is possible via current, resistive, or duty ratio control.
Abstract: A switched capacitor DC-DC power converter topology which consists of n stages of semiconductor switches and capacitors is described The switches connect the capacitors across the input source during the charging phase and then across the load during the discharge phase to step down the input voltage by a nominal ratio n Further control of the output voltage is possible via current, resistive, or duty-ratio control Based on the observation that the ripple on the capacitor voltages is generally linear in practice, state-space averaging is used to derive the average state-space equations for a generalized n-stage switched capacitor converter circuit Both exact and approximate equations which are useful for design are derived for the practical performance parameters A design procedure based on these equations is described The analytical results have been verified by extensive simulation by PSPICE >

Proceedings ArticleDOI
04 Oct 1992
TL;DR: In this article, 15 active power factor correction (PFC) topologies with nonpulsated input current are presented, and the normalized set of auxiliary parameters is derived for convenient comparisons of current and voltages stresses as well as conduction losses.
Abstract: Fifteen active power factor correction topologies with nonpulsated input current are presented. For convenient comparisons of current and voltages stresses as well as conduction losses, the normalized set of auxiliary parameters is derived. These parameters are shown to be simple functions of the ratio of the line voltage amplitude and DC output voltage. Since the choice of any particular topology usually depends on many application-specific factors rather than judging various power factor correction (PFC) topologies, a possibly complete class of these structures is presented, together with evaluation. >

Journal ArticleDOI
29 Jun 1992
TL;DR: In this article, an active power filter is proposed for balancing unbalanced loads in a three-phase, PWM (pulsewidth-modulated) AC-to-DC converter with inductive energy storage.
Abstract: An active power filter is proposed for balancing unbalanced loads. A three-phase, PWM (pulse-width-modulated) AC-to-DC converter topology with inductive energy storage is controlled to continuously inject desired negative sequence currents into the distribution system to achieve balancing of continuously varying unbalanced loads. The principle of operation is as follows: the negative sequence components of the load currents are measured in magnitude and in phase and the PWM-controlled active power filter is controlled to inject currents opposite to these quantities, thereby achieving the balancing function. The operation of the proposed system and the selection of the active power filter components are discussed in detail. Experimental filter operation is verified for an unbalanced load. >

Journal ArticleDOI
TL;DR: In this paper, the authors describe a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1- mu m CMOS technology.
Abstract: Two-step flash architectures are an effective means of realizing high-speed high-resolution analog-to-digital converters (ADCs) because they can be implemented without the need for operational amplifiers having either high gain or a large output swing. Moreover, with conversion rates approaching half those of fully parallel designs, such half-flash architectures provide both a relatively small input capacitance and low power dissipation. The authors describe the design of a 12-b 5-Msample/s A/D converter that is based on a two-step flash topology and has been integrated in a 1- mu m CMOS technology. Configured as a fully differential circuit, the converter performs a 7-b coarse flash conversion followed by a 6-b fine flash conversion. Both analog and digital error correction are used to achieve a resolution of 12 b. The converter dissipates only 200 mW from a single 5-V supply and occupies an area of 2.5 mm * 3.7 mm. >

Journal ArticleDOI
01 Mar 1992
TL;DR: The space- vector-modulation (SVM) technique for control of the 3-phase/3-phase matrix convertor is presented and the FCC space-vector modulator is experimentally verified.
Abstract: Novel research results on control of forced-commutated cycloconvertors (FCCs)with matrix topology are summarised. The space-vector-modulation (SVM) technique for control of the 3-phase/3-phase matrix convertor is presented. The SVM technique provides FCC output voltages of any frequency, from zero to a maximum value constrained by the switching frequency, and any amplitude, up to √(3)/2 of the input voltage amplitude, without low-frequency harmonics. Time-domain-simulation results and spectral analysis of the output voltages and input currents are shown. The space-vector modulator is digitally implemented in a microprocessor system with reduced real-time computation. The switching times are precalculated offline and the results are stored in EPROMs. A multistepped switching procedure for safe control of the matrix-convertor switches is also presented. The safe-control algorithm is implemented with a sequential circuit by using a PROM lookup table. The FCC space-vector modulator is experimentally verified.

Proceedings ArticleDOI
29 Jun 1992
TL;DR: A 20 kVA direct DC/LFAC dual active bridge (DAB) power converter projected for operation at 100 kHz with insulated gate bipolar transistor (IGBT) switches is presented in this article.
Abstract: A 20 kVA direct DC/LFAC dual active bridge (DAB) power converter projected for operation at 100 kHz with insulated gate bipolar transistor (IGBT) switches is presented. It has dual-angle, constant-frequency phase shift control, and is soft switched in a large part of the output V-I plane. It also has a high performance digital control system. The topology and its properties are presented. The control strategy and regulation of the loop are examined. Experimental results are shown for both a small-scale model and a full-scale converter. >

Proceedings ArticleDOI
01 Jun 1992
TL;DR: In this article, a power amplifier topology was demonstrated in a microwave monolithic integrated circuit (MMIC) implementation with GaAs MESFETs, where unit cells are both parallel and series combined.
Abstract: A power amplifier topology was demonstrated in a microwave monolithic integrated circuit (MMIC) implementation with GaAs MESFETs. This topology overcomes several limitations of the traditional approach of paralleling of power transistor unit cells. In the new topology, unit cells are both parallel and series combined. The benefits include higher input and output impedances, broadband power matched interstage networks, and high voltage biasing at reduced DC current. Measured results on a MMIC and a hybrid power amplifier implemented with this technique are presented. >

Proceedings ArticleDOI
04 Oct 1992
TL;DR: In this article, the authors proposed an improved version of the known PWM controller topologies that can become a practical alternative to line-commutated AC controllers, including the use of typical unilateral switches, typical gating patterns, and reliability enhancing bypass capacitors.
Abstract: The authors propose an improved version of the known pulse width modulation (PWM) controller topologies that can become a practical alternative to line-commutated AC controllers. The improvements include the use of typical unilateral switches, typical gating patterns, and reliability enhancing by-pass capacitors. The authors also present the analysis and design of the proposed converter topology, with key theoretical results verified experimentally on a 10 kVA breadboard. >

Journal ArticleDOI
TL;DR: An enhanced fully differential folded-cascode operational-amplifier topology that achieves improved DC gain and common-mode rejection without sacrificing slew rate is presented and is verified by simulations and preliminary experimental results.
Abstract: An enhanced fully differential folded-cascode operational-amplifier topology that achieves improved DC gain and common-mode rejection without sacrificing slew rate is presented. The large-signal operation of the new topology is completely symmetric, providing equal positive and negative slew-rate behavior by making use of current mirrors rather than current sources as normally found in full differential folded-cascode op-amps. An additional advantage of the enhanced topology is that its common-mode output impedance is a factor of g/sub m/r/sub o/ (typically 1-2 orders of magnitude) lower than the differential-mode output impedance, significantly improving the common-mode rejection ratio. The predicted performance is verified by simulations and preliminary experimental results. >

Proceedings ArticleDOI
01 Jul 1992
TL;DR: The model of asynchronous, dynamic-topology network is equivalent to the synchronous, static protocols that can withstand arbitrary link delays and changing topology at the expense of only polylogarithmic blowup in the running time, the number of messages, and the space requirement.
Abstract: The computational power of different communication models is a fundamental question in the theory of distributed computation. For example, in the synchronous model messages are assumed to be delivered within one time unit, whereas in the asynchronous model message delays may be arbitrary. Another important parameter of the model is the assumptions about the topology. In the dynamic topology model, links are assumed to crash and recover dynamically, but their status is known to the incident node processors. A meaningful computation can be carried out if the topology stabilizes for a sufficiently long period.In this paper we show that the model of asynchronous, dynamic-topology network is equivalent, up to polylogarithmic factors, to the synchronous, static protocols that can withstand arbitrary link delays and changing topology at the expense of only polylogarithmic blowup in the running time, the number of messages, and the space requirement. Previous methods entailed a linear blowup in at least one of these resources.The generality of our method is demonstrated by a series of improvements for important applications, including Breadth First Search, computing compact efficient routing tables, and packet routing on asynchronous networks.

Journal ArticleDOI
TL;DR: In this paper, a class-E resonant low dv/dt rectifier is analyzed and experimentally tested for high-frequency applications such as resonant DC-to-DC converters.
Abstract: A class-E resonant low dv/dt rectifier is analyzed and experimentally tested. All major parasitic reactive components are included in the rectifier topology. The diode capacitance and the leakage inductance of the isolation transformer and lead inductances are absorbed into the resonant inductance. Therefore, the rectifier is suitable for high-frequency applications such as resonant DC-to-DC converters. The rectifier is driven by a sinusoidal voltage source. Equations governing the circuit operation are derived using Fourier techniques. Experimental results are obtained at 1 MHz and an output voltage of 5 V. The design equations show good agreement with the measured circuit performance. >

Journal ArticleDOI
01 Oct 1992
TL;DR: In this article, a general topology is given to implement sinusoidal oscillators by using operational transconductance amplifier capacitor (OTA-C) techniques, and five different structures are presented, taking into account the CMOS OTAs dominant non-idealities.
Abstract: A systematic approach to derive practical CMOS sinusoidal oscillators is presented. A general topology is given to implement sinusoidal oscillators by using operational transconductance amplifier capacitor (OTA-C) techniques. To illustrate the proposed approach five different structures are presented from this general topology and analysed, taking into account the CMOS OTAs dominant non-idealities. Building blocks are presented for amplitude control, both by automatic gain control (AGC) schemes and by limitation schemes. Experimental results from 3 μm and 2 μm CMOS (MOSIS) prototypes showing oscillation frequencies up to 69 MHz are included. The amplitudes can be adjusted between 1 V peak-to-peak and 100 mV peak-to-peak. Total harmonic distortions (THD) from 2.8% down to 0.2% have been experimentally measured in the laboratory. A frequency tuning loop for these structures is introduced that provides a precise, temperature and parasitic independent frequency-to-voltage relationship. Experimental results for the tuning loop are presented.

Journal ArticleDOI
TL;DR: Physical defects widely encountered in today's CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter.
Abstract: Physical defects widely encountered in today’s CMOS processes (bridges, gate oxide short (gas) and floating gates) are modeled taking into account the topology of the defective circuit and the parameters of the technology. These models are used to simulate at electrical level the behavior of a simple 3-inverter chain with a defective inverter. The results are compared with experimental data of integrated circuits fabricated with intentional defects. The influence of the characteristics of each defect on I DDQ has been investigated by electrical simulation and experimentation.

Proceedings ArticleDOI
01 May 1992
TL;DR: The authors describe a methodology for designing interconnected local area network/metropolitan area network (LAN-MAN) networks with the objective of minimizing the average network delay and find the solutions are not very far from the global minimum.
Abstract: The authors describe a methodology for designing interconnected local area network/metropolitan area network (LAN-MAN) networks with the objective of minimizing the average network delay. They consider IEEE 802.3-5 LANs interconnected by transparent bridges. These bridges are required to form a spanning tree topology. The optimization algorithm for finding a minimum delay spanning tree topology is based on simulated annealing. In order to measure the quality of the solutions, a lower bound for the average network delay is found. The comparison of results with this lower bound and several other goodness measures shows that the solutions are not very far from the global minimum. The authors extend the present algorithm for finding minimum delay LAN-MAN topologies consisting of fiber distributed data interface (FDDI) MANs or switched multi-megabit data service (SMDS) interconnecting several clusters of bridged LANs. >

Proceedings ArticleDOI
01 Jul 1992
TL;DR: A mixed-integer nonlinear programming (MINLP) approach to cell-level analog circuit synthesis, allowing simultaneous topology selection and parameter selection, is presented.
Abstract: A mixed-integer nonlinear programming (MINLP) approach to cell-level analog circuit synthesis, allowing simultaneous topology selection and parameter selection, is presented. The problem formulation uses integer variables to model topology choices and continuous variables for the design parameters such as device sizes and bias voltages. Examples using a branch and bound approach to efficiently solve the MINLP problem for CMOS two-stage operational amplifiers are given. >

Proceedings ArticleDOI
07 Sep 1992
TL;DR: The authors present two methods for optimizing the topology of given power/ground networks on VLSI chips that yield a reduction of thePower/ground routing area and do not degrade the reliability of the power/Ground network.
Abstract: The authors present two methods for optimizing the topology of given power/ground networks on VLSI chips. The cycle-reduction-method removes cycles and root paths (paths between two pads) in a general power/ground graph. The node-reduction-method removes branching nodes (nodes incident to more than two branches) in a power/ground tree. Both methods yield a reduction of the power/ground routing area and do not degrade the reliability of the power/ground network. Small examples to explain the procedures are included and experimental results for benchmark circuits are presented. >

Patent
Marcus K Dasilva1
12 Aug 1992
TL;DR: In this paper, a vector-locked loop is disclosed having a topology somewhat similar to two cross coupled phase-locked loops, but wherein both magnitude and phase are used as feedback signals.
Abstract: A vector locked loop is disclosed having a topology somewhat similar to two cross coupled phase locked loops, but wherein both magnitude and phase are used as feedback signals. The output signal is generated by combining the outputs of two VCOs in a combiner network. This output signal is fed back to the input, where phase and magnitude detectors are used to generate error signals. These error signals are processed to yield control signals for controlling the frequencies of the two VCOs. The vector locked loop can be adapted for a number of applications, including frequency translation, modulation (phase, amplitude or arbitrary), and high efficiency linear power amplification.


Patent
Norman R. Scheinberg1
03 Mar 1992
TL;DR: In this paper, a monolithic upconverter integrated circuit is described, which performs the first frequency conversion of a dual conversion cable television (CATV) receiver, including three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator.
Abstract: A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver. The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator. Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer. A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss. On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package. A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing.

Proceedings ArticleDOI
01 Jun 1992
TL;DR: In this paper, the authors present a systematic experimental examination of the validity of basic large-signal modeling assumptions by subjecting measured S-parameter data versus bias from MESFETs and HEMTs (high electron mobility transistors) to various mathematical operations of vector analysis.
Abstract: The authors presents a systematic experimental examination of the validity of basic large-signal modeling assumptions by subjecting measured S-parameter data versus bias from MESFETs and HEMTs (high electron mobility transistors) to various mathematical operations of vector analysis Several approaches are used to determine the degree to which pairs of device nonlinearities can be accurately modeled by charge-based nonlinear capacitors, voltage-controlled current sources, and higher-order elements arranged in a standard equivalent circuit topology Implications are discussed for such circuit modeling concepts as terminal charge conservation and its extension to other state-functions >