Showing papers on "Topology (electrical circuits) published in 1993"

Topology control for multihop packet radio networks

Abstract: A distributed topology-control algorithm has been developed for each node in a packet radio network (PRN) to control its transmitting power and logical neighbors for a reliable high-throughput topology. The algorithm first constructs a planar triangulation from locations of all nodes as a starting topology. Then, the minimum angles of all triangles in the planar triangulation are maximized by means of edge switching to improve connectivity and throughput. The resulting triangulation at this stage, the Delaunay triangulation, can be determined locally at each node. The topology is modified by negotiating among neighbors to satisfy a design requirement on the nodal degree parameter. Simulations show that the final topology is degree-bounded, has a rather regular and uniform structure, and has throughput and reliability that are greater than that of a number of alternative topologies. >

Circuit topologies for single-phase voltage-doubler boost rectifiers

Abstract: A new family of single-phase voltage-doubler PWM (pulse width modulated) boost rectifiers is presented. By examining the switching states of several standard single-phase boost rectifier circuits, three characteristic PWM voltage switching patterns are identified: unipolar PWM; bipolar PWM; and phase-adjusted unipolar PWM. From this analysis, an equivalent family of voltage-doubler rectifiers is derived. When high output voltages are required, voltage-doubler rectifiers are shown to be able to generate AC line currents with the lowest current distortion. The circuits presented are examined using circuit simulators and experimental results. >

A novel single-phase power factor correction scheme

Abstract: A single-phase power factor correction scheme is proposed based on the power flow analysis. It is found that the conventional power factor correction (PFC) circuit must be designed to handle the rated power, although its purpose is only for power factor correction. With the proposed scheme, the PFC circuit is in parallel with the major power flow path, thus reducing its size and weight compared to a conventional two-cascade-stage scheme. A prototype circuit is built and tested to verify this concept. >

A comparative evaluation of harmonic reduction techniques in three-phase utility interface of power electronic loads

Abstract: Power electronic loads inject harmonic currents into the utility system. This paper presents a comparative evaluation of harmonic reduction techniques which satisfy the current harmonic limits specified by the IEEE Standard 519, and at the same time provide a regulated DC output voltage. The techniques considered include active and hybrid filters, and various current waveshaping approaches for a three-phase utility interface. These techniques are compared in terms of their complexity (number of switches) and their component ratings. Based on the application requirements and the cost of active and passive components, this paper enables the estimation of the minimum cost topology. >

Isolated boost circuit for power factor correction

Abstract: To provide a 48 volt DC bus for distributed power systems, AC-DC power converters with high power factor and isolation are required. Instead of using a conventional two stage scheme which has a boost front end followed by a DC-DC converter, a boost derived topology is chosen to achieve high power factor, isolation, and voltage step down. A newly proposed technology of soft switched insulated gate bipolar transistors (IGBTs) is used for this application to reduce the IGBT switching loss and achieve low conduction loss. The design considerations of the power stage and the control circuit are provided. A prototype converter is built to show the feasibility of the single stage scheme. >

Unity PF current-source rectifier based on dynamic trilogic PWM

Abstract: One remaining step in perfecting the stand-alone, unity power factor, regulated current-source pulse-width-modulated (PWM) rectifier is to reduce cost, by bringing the twelve-valve converter (consisting of three single-phase full bridges that operate with two-level or bilogic PWM) to the six-valve bridge. However, the six-valve topology requires a three-level or trilogic PWM strategy that can handle feedback signals. A general method of translating three-phase biologic PWM signals into three-phase trilogic PWM signals is presented. The method of translation retains the characteristics of the bilogic PWM, including the frequency bandwidth. Experiments show that the trilogic PWM signals produced by the method can handle not only stabilizing feedback signals but also signals for active filtering. >

Method and apparatus for transforming an arbitrary topology collection of nodes into an acyclic directed graph

Abstract: A system and method are described which take an arbitrarily assembled collection of nodes on a bus or network and imposes an optimized hierarchical tree structure where there is only one root node. Nodes having both parent and child nodes are considered branch nodes while nodes having only parent nodes are leaf nodes. Loops or cycles in the physical topology are resolved into a logical topology that is acyclic and directed. A signaling scheme is developed in which nodes, via on board communications hardware, signal all connected nodes and respond accordingly until hierarchical relationships are established. Cycles are resolved by intelligently breaking links to yield an acyclic graph. Direction is established by each node recognizing its parent/child status with respect to connected nodes until a single node is established as a root node.

Analysis of series-parallel resonant converter

Abstract: A frequency-domain steady-state analysis is given for a series-parallel resonant converter (SPRC) operating in the continuous conduction mode (CCM) using Fourier series techniques. Equations for performance parameters are derived under steady-state conditions to provide simple design tools. The topology of the SPRC combines the advantageous properties of both the series resonant converter (SRC) and the parallel resonant converter (PRC). The key results of the work are: a novel half-wave rectifier SPRC, conditions for obtaining high part-load efficiency; and several boundary frequencies and limiting conditions such as the capacitive/inductive load boundary and open-circuit and short-circuit cases. Experimental results measured for an 80-W converter above the resonance at different load resistances and input voltages show excellent agreement with the theoretical performance predicted by the equations. >

Identification of topology errors in power system state estimation

Abstract: This paper deals with the processing of topology errors in power system state estimation. An algorithm is proposed for determining a correlation index between symptoms of anomalies in the estimation process and measurements related to the network-elements suspected of being misconfigured. A method based on such an algorithm enables one to recognize the occurrence of topology errors in the real-time modeling process and to identify the misconfigurations. The proposed method has been tested on three different power systems, including a realistic network which is part of the Southern Brazil interconnected system, for various types of topological errors (inclusion, exclusion and bus-split errors). >

Integrated continuous-time balanced filters for 16-b DSP interfaces

Abstract: A fully integrated, low-distortion, balanced, continuous-time filter fabricated in 5-V, 1.6- mu m CMOS is presented. Active RC structures are used in a leapfrog topology, with time constants set by integrated passive resistors and capacitors. Accurate tuning is achieved by selection of capacitor elements under the control of a new calibrator circuit. With a 2-V/sub rms/ differential input and output, the filter achieves -94-dB THD (total harmonic distortion) and 95-dB signal-to-noise ratio. Tuning accuracy is maintained to within +or-5% of nominal over the commercial temperature range. >

Average simulation of PWM converters by direct implementation of behavioral relationships

Abstract: Average modeling of PWM power converters is reexamined in the light of the behavioral dependent sources now included in modern versions of electronic circuit simulators. A topology independent behavioral model is developed to emulate the operation of PWM converters in voltage and current modes, for continuous and discontinuous inductor current cases. It is shown that, in general, the operation of the switching part involves three behavioral blocks, i.e., the generic switched inductor model (GSIM), the duty cycle generator (DCG), and the inductor current generator (ICG). Explicit expressions and equivalent circuits are developed for all possible modes of operation. >

Analysis and design of boost zero-voltage-transition PWM converter

Abstract: The analysis and design of a boost zero-voltage-transition (ZVT) PWM power converter is carried out by means of the normalized state-plane-trajectory method. This topology has the advantages of constant switching frequency, soft switching on all the active switches, the fixed voltage stresses under all load situations. The design procedure is demonstrated by using a specific example. Experimental results are given to confirm the authors' analytical work. >

Current-sourcing push-pull parallel-resonance inverter (CS-PPRI): theory and application as a fluorescent lamp driver

Abstract: A novel topology, current-sourcing push-pull parallel-resonance inverter (CS-PPRI), is investigated theoretically and experimentally. The proposed power stage is built around a current fed push-pull inverter. The main features of the proposed inverter are a load-independent output current and zero voltage switching (ZVS). It is suggested that the proposed CS-PPRI is a viable alternative for realizing electronic ballasts for low and high intensity discharge lamps. >

Distributed computing with high-speed optical networks

Abstract: An environment that uses wavelength division multiplexing techniques and optical switching and processing to provide large bandwidths, short delays, and multiple data streams for distributed processing is described. The focus is on the interrelationship between application needs and network services. The system level, a conceptual layer designed to bridge the gap between application requirements and underlying high-speed network services, is proposed. The system level is a logical view of the physical network represented by a virtual topology projected onto the physical network. Embedding this virtual topology introduces many new problems and performance tradeoffs into the design of the network. A few of these problems are outlined, and some initial research efforts in this area are discussed. The physical network level, the collection of optical fiber links interconnecting the nodes in the network, and the application level, a logical view of an application's computational topology and representation of the application's communication and computing requirements, are also described. >

Economic single-phase to three-phase converter topologies for fixed and variable frequency output

Abstract: Several component-minimized circuit topologies for single-phase to three-phase conversion are proposed. The topologies employ fewer semiconductor devices and generate high-quality output voltages. Suitable modification to achieve active input current shaping is illustrated in detail. Analysis and simulation of the proposed schemes are carried out to show the high-performance features. Suitable guidelines for the selection of filter components and for facilitating circuit design are presented. Selected results are verified experimentally on laboratory prototype converters. >

Analysis and design of a wide input range power factor correction circuit for three-phase applications

Abstract: A combined buck and boost topology power factor correction circuit which can operate with input voltages from 150 to 540 V is presented. The design and analysis of the operation and dominant losses of this circuit are given. The features of the topology are compared with those of a standard boost power factor correction circuit. >

Topological design of interconnected LAN/MAN networks

Abstract: The authors describe a methodology for designing interconnected LAN/MAN networks with the objective of minimizing the average network delay. They consider IEEE 802 standard LANs interconnected by transparent bridges. These bridges are required to form a spanning tree topology. The authors propose a simulated annealing-based algorithm for designing minimum delay spanning tree topologies. In order to measure the quality of the solutions, a lower bound for the average network delay is found. The algorithm is extended to design the overall LAN/MAN topology consisting of a MAN or high-speed data service interconnecting several clusters of bridged LANs. Comparison with the lower bound and several other measures show that the solutions are not very far from the global minimum. >

Imbricated Cells Multi-Level Voltage-Source Inverters for High Voltage Applications

Abstract: SummaryIn the field of High Voltage Power Conversion, various techniques have been developped to use series-connected switches.Plain series connection of switches is the first solution and its drawbacks are now well-known (static and dynamic voltage sharing difficulties that require selecting paired switches or using sophisticated control techniques, high dV/dts generated by the synchronous commutation of all the switches, output waveform that does not benefit from the increased number of switches...).The “neutral point clamped” technique introduced in the early 80s improves voltage sharing and dV/dts, and gives a three-level output waveform.More recently a new multilevel topology has been introduced; compared to former techniques, it really solves the problem of voltage sharing and dV/dts, and gives a three-level output waveform with cancellation of the harmonic at the switching frequency.In this paper, it is shown that this technique can be easily generalized to voltage-source inverter legs with any num...

Power conversion array applying small sequentially switched converters in parallel

Abstract: Decreased input and output ripple current and ripple voltage on a switched mode power conversion array is realized at high power levels and frequencies by coupling an input power signal across an input capacitance to which a plurality of smaller power converter circuits are coupled in parallel. The converter circuits may have any topology now known or later devised. Each of the converter circuits are sequentially operated in a phase shifted manner across the period of the conversion frequency in a time overlapping relationship. For example, if there are N converters and the period of the conversion frequency is T, each converter circuit is triggered or switched at a phase shift corresponding to a time increment of T/N delayed with respect to the preceding or subsequent converter. The output of each of the converters is then coupled in parallel to an output capacitance. The operation of the converters may each be regulated in any manner now known or later devised and are shown in the illustrated embodiment as being pulse width modulated to provide a regulated output.

An input-free V/sub T/ extractor circuit using a two-transistor differential amplifier

Abstract: A three-terminal circuit (power, ground, and output) that provides a DC output voltage equal to the MOS threshold voltage V/sub T/ is presented. The circuit uses the four-terminal extractor topology of Z. Wang (1992), but it adds self-biasing and a two-transistor differential amplifier to provide a ground-referenced output voltage. >

Nodal analysis of switched-current filters

Abstract: An efficient and relatively simple approach to the systematic analysis of ideal, or near-ideal, switched-current filters is described. The technique is based on the nodal analysis of a linear resistive network that models the behavior of the filter for small signals, allowing the use of any practical topology and the inclusion of important imperfections, as output resistances of MOS transistors, series resistances of current-conducting switches, and parasitic capacitances. Techniques for frequency-domain analysis, z-transform calculations, time-domain analysis, and frequency-domain sensitivity analysis are discussed. The method is not restricted to the analysis of the particular structures of switched-current filters. It can be easily generalized for the analysis of a wide class of periodically switched RC-active circuits, where it is assumed that the circuits stabilize between the switching instants. >

Analysis of switching devices with bond graphs

Abstract: Modelling and simulation of switching devices with bond graphs is a subject which has no totally satisfying solutions. In this paper, switching devices are represented by flow or effort sources, with a variable circuit topology at switching time. For the simulation, the usual method uses causality resistors to insure integral causality to energy storage elements. The choice of those resistors is quite arbitrary and can lead to stiff systems. We propose, for linear systems, an approach without such resistors. When components lose the integral causality, the order of the state vector changes, provoking the use of pulse variables. A solution is proposed to compute the amplitude of the pulse and the value of the new variables.

Constant-G/sub m/ rail-to-rail common-mode range input stage with minimum CMRR degradation

Abstract: The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2- mu m feature size are given. >

Class E full-wave low dv/dt rectifier

Abstract: An analysis and experimental verification for a Class E full-wave current-driven low dv/dt rectifier are given. Basic parameters of the circuit are derived using the time-domain analysis and Fourier series techniques. The rectifier diodes turn on and off at low dv/dt, yielding low switching noise and low switching losses. Diode parasitic capacitances do not adversely affect the circuit operation. The absolute value of di/dt is limited at diode turn-off, significantly reducing the reverse recovery current. The rectifier input voltage waveform differs only slightly from an ideal sinusoid, resulting in a low total harmonic distortion. The circuit has theoretically zero-ripple voltage and, therefore, zero loss in the equivalent series resistance (ESR) of the filter capacitor. The Class E full-wave topology has lower diode conduction loss than the Class E half-wave rectifier. The efficiency is almost constant over the load range from 10% to 100% of the full load. The rectifier offers high-power density and high-frequency rectification and is suitable for low-voltage and high-current applications, as shown by experimental results given for a 75-W rectifier which was operated at 1 MHz with an output of 5 V and 15 A. The theoretical and experimental results were in good agreement. >

Practical experience with rule-based on-line topology error detection

Abstract: This paper describes the experience gained in the integration of a rule-based topology error detection algorithm into an existing energy management system (EMS) in a central European control center. The expected and actual results have been very encouraging and at the same time new ideas from the utility have been incorporated to increase the effectiveness of the algorithm for the operator. >

Synchronous-rectification type control for direct current motors and method of making

Abstract: A MOSFET (50, 51) control topology and a physical structure for a motor control which provide a more efficient and economic DC motor control are disclosed. The control topology introduces a synchronous-rectification technique wherein free-wheel diodes are replaced with MOSFET (50, 51) devices that are switched on and off by a logic circuit (38) so that they are conductive for commuting motor current during periods that the motor (24) current supply is switched off. The physical structure and method of assembling a DC motor control (33) eliminate time consuming assembly techniques while ensuring effective waste heat exchange between electronic components (46, 50, 51) and a heat sink (96) of the control (33) by providing quick-install spring retainers (110) for urging the components (46, 50, 51) into heat conducting contact with the heat sink (96). The physical structure also provides for high density packing of electronic components (46, 50, 51) in the control (33).

Abstract reduction and topology

Abstract: reduction and topology Ferrer, W.; Severi, P.G. Published: 01/01/1993 Document Version Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication Citation for published version (APA): Ferrer, W., & Severi, P. G. (1993). Abstract reduction and topology. (Computing science notes; Vol. 9335). Eindhoven: Technische Universiteit Eindhoven. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policy If you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. Download date: 29. Dec. 2018 Eindhoven University of Technology Department of Mathematics and Computing Science Abstract Reduction and TopologyReduction and Topology

Network hub for maintaining node bandwidth in a single-node network

Abstract: A hub network system is provided for communication between nodes. The system can be used, e.g., when one node can be configured for baseband bus topology communication, such as LocalTalk™ communication. The node can communicate using the entire bandwidth of the medium, such as 230 Kbps bandwidth, even though other nodes are connected to the network using the hub card. Preferably, the hub card includes a multiprocessor system with a shared memory for providing high internal effective bandwidth communication, such as 15 Mbps communication. A proxy scheme is provided so that the hub topology is transparent to any node which can operate as though it were configured in a bus topology.

A trip-based multicasting model for wormhole-routed networks with virtual channels

Abstract: This paper considers the single-source and multi-source multicasting problem in wormhole-routed networks. A general trip-based model is proposed for any network having at least 2 virtual channels per physical channel. The underlying concept of this model is a node sequence called skirt, which always exists in graphs of any topology. The strength of this model is demonstrated by its capabilities: (a) the resulting routing scheme is simple, adaptive, distributed and deadlock-free; (b) the model is independent of the network topology, regular or irregular; (c) the minimum number of virtual channels required is constant as the network grows in size; and (d) it can tolerate faults easily. Using 2 virtual channels/physical channel, it is shown how to construct a single trip in faulty hypercubes and multiple trips in fault-free meshes. Simulation experimental results indicate the potential of the model to tolerate faults with very little performance degradation and to reduce multicast latency with multiple trips. >

Why multi-load topology designs based on orthogonal microstructures are in general non-optimal

Abstract: It is well established that for a compliance constraint, the optimal topology of perforated plates under plane stress tends to that for least-weight trusses (Michell structures) as the “volume fraction” (i.e. the ratio material volume/available volume) approaches zero. It is shown in this note that for two loading conditions the optimal bar orientations for Michell structures are in general non-orthogonal and hence the assumption of orthogonal microstructures in multi-load plate topology optimization must lead to erroneous results.