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Showing papers on "Topology (electrical circuits) published in 1994"


Journal ArticleDOI
TL;DR: In this article, the adjoint variable is used for sensitivity analysis and the linear programming method is used to obtain the optimal topology, which can handle various problems, for example, multiple objective functions and multiple design criteria.

271 citations


Journal ArticleDOI
TL;DR: In this article, generalized half-bridge and full-bridge resonant converter topologies with two, three and four energy storage elements are presented and compared with typical second-and third-order series resonant converters, whereas the fourth-order topology is based on the approximate analysis.
Abstract: Generalized half-bridge and full-bridge resonant converter topologies with two, three and four energy storage elements are presented. All possible circuit topologies for such converters under voltage/current driven and voltage/current sinks are discussed. Many of these topologies have not been investigated in open literature. Based on their circuit element connections and source and load excitation types, these topologies are classified into resonant and nonresonant topologies and on their physical realizability. Comparison based on exact steady state analysis are given for typical second- and third-order series resonant converters whereas the fourth-order topology is based on the approximate analysis. >

229 citations


Journal ArticleDOI
TL;DR: In this article, the authors present a self-consistent set of algorithms for the numerical computation of noise effects in forced and autonomous nonlinear microwave circuits using piecewise harmonic balance.
Abstract: This paper presents a self-consistent set of algorithms for the numerical computation of noise effects in forced and autonomous nonlinear microwave circuits. The analysis relies upon the piecewise harmonic-balance method, and thus retains all the peculiar advantages of this technique, including general-purposeness in the widest sense. The noise simulation capabilities include any kind of forced or autonomous nonlinear circuit operated in a time-periodic large-signal steady state, as well as microwave mixers of arbitrary topology. The limitations of the traditional frequency-conversion approach to noise analysis are overcome. The analysis takes into account the thermal noise generated in the passive subnetwork, the noise contributions of linear and nonlinear active devices, and the noise injected by sinusoidal driving sources of known statistical properties. The nonlinear noise models of two representative families of microwave devices (FET's/HEMT's and Schottky-barrier diodes) are discussed in detail, and several applications are illustrated. >

199 citations


Patent
05 Aug 1994
TL;DR: In this paper, the authors propose a power converter circuit that includes a controller, at least two transistors and an output network that provides impedance matching and operating point stabilization functions, thus reducing radiated noise and minimizing switching losses.
Abstract: A power converter circuit provides low conversion losses, low generated noise and output power controllability. The circuit includes a controller, at least two transistors and an output network that provides impedance matching and operating point stabilization functions. The output network also enables zero voltage switching of the transistors, thus reducing radiated noise and minimizing (and possibly eliminating almost completely) switching losses. The controller circuitry includes an oscillator which is capable of self synchronizing to the resonant frequency of the components of the output network. Power modulation (e.g., for dimming of a lamp) is accomplished simply by desynchronizing and increasing the oscillator frequency. Thus, the control architecture allows the use of external parts of lower precision and cost while providing dimming capability in a single stage.

182 citations


Journal ArticleDOI
Kumar N. Sivarajan1, Rajiv Ramaswami1
TL;DR: De Bruijn graphs are proposed as logical topologies for multihop lightwave networks consisting of all-optical routing nodes interconnected by point-to-point fiber links and a physical topology based on a de Bruijn graph can support a large number of stations using a relatively small number of wavelengths.
Abstract: Proposes de Bruijn graphs as logical topologies for multihop lightwave networks. After deriving bounds on the throughput and delay performance of any logical topology, the authors compute the throughput and delay performance of de Bruijn graphs for two different routing schemes and compare it with their bounds and the performance of shufflenets. For a given maximum nodal in- and out-degree and average number of hops between stations, a logical topology based on a de Bruijn graph can support a larger number of stations than a shufflenet and this number is close to the maximum that can be supported by any topology. The authors also propose de Bruijn graphs as good physical topologies for wavelength routing lightwave networks consisting of all-optical routing nodes interconnected by point-to-point fiber links. The worst-case loss experienced by a transmission is proportional to the maximum number of hops (diameter). For a given maximum nodal in- and out-degree and diameter, a physical topology based on a de Bruijn graph can support a large number of stations using a relatively small number of wavelengths. >

174 citations


Proceedings ArticleDOI
12 Jun 1994
TL;DR: Algorithms are developed so that the WDM-based network architecture will provide a high aggregate system capacity due to spatial reuse of wavelengths, and support a large and scalable number of users, given a limited number of wavelengths.
Abstract: Explores design principles for next generation optical wide-area networks, employing wavelength-division multiplexing (WDM), and targeted to nationwide coverage. This almost-all-optical network will exploit wavelength multiplexers and optical switches in routing nodes, so that arbitrary virtual topologies may be imbedded on a given physical network. The virtual topology, which is packet switched and which consists of a set of all-optical lightpaths, is set up to exploit the relative strengths of both optics and electronics viz. packets of information are carried by the virtual topology "as far as possible" in the optical domain, but packet forwarding from lightpath to lightpath is performed via electronic switching, whenever required. Algorithms are developed so that the WDM-based network architecture will (a) provide a high aggregate system capacity due to spatial reuse of wavelengths, and (b) support a large and scalable number of users, given a limited number of wavelengths. The authors illustrate their approaches by employing experimental traffic statistics collected from NSFNET. >

155 citations


Journal ArticleDOI
TL;DR: In this article, a representative switched-capacitor DC-DC converter topology is presented, circuit operation is explained, and control strategies are identified, and state-space averaging is used to analyze steady state performance and to develop control criteria and design equations.
Abstract: A representative switched-capacitor DC-DC converter topology is presented, circuit operation is explained, and control strategies are identified. State-space averaging is used to analyze steady-state performance and to develop control criteria and design equations. The analytical results are verified by SPICE simulation. >

149 citations


Journal ArticleDOI
TL;DR: This paper discusses the reconfiguration phase which is the transition between the current logical connection diagram and a target diagram, and considers here an approach where the network reaches some target connectivity graph through a sequence of intermediate connection diagrams, so that two successive diagrams differ by a single branch-exchange operation.
Abstract: Some of today's telecommunications networks have the ability to superimpose some form of logical connectivity, or virtual topology, on top of the underlying physical infrastructure. According to the degree of independence between the logical connectivity and the physical topology, the network can dynamically adapt its virtual topology to track changing traffic conditions, and cope with failure of network equipment. This is particularly true for lightwave networks, where a logical connection diagram is achieved by assignment of transmitting and receiving wavelengths to the network stations that tap into, and communicate over, an infrastructure of fiber glass. Use of tunable transmitters and/or receivers allow the logical connectivity to be optimized to prevailing traffic conditions. With rearrangeability having thus emerged as a powerful network attribute, this paper discusses the reconfiguration phase which is the transition between the current logical connection diagram and a target diagram. We consider here an approach where the network reaches some target connectivity graph through a sequence of intermediate connection diagrams, so that two successive diagrams differ by a single branch-exchange operation. This is an attempt at logically reconfiguring the network in a way that is minimally disruptive to the traffic. We propose and compare three polynomial-time algorithms that search for "short" sequences of branch-exchange operations, so as to minimize the overall reconfiguration time. For networks made of up to 40 stations, theoretical and simulation results show that, when a randomly selected diagram is to be changed to another randomly chosen diagram, the average number of branch-exchange operations required grows linearly with the size of the network. >

126 citations


Journal ArticleDOI
TL;DR: This contribution describes a procedure for determining the optimal topology of a static three-layer neural network based on a canonical decomposition technique that establishes a link between the number of neurons in each hidden layer and the dimensions of the subspaces of the canonical decompositions.

116 citations


Journal ArticleDOI
TL;DR: In this paper, a lumped-component equivalent circuit has been developed to model the electric behavior of any two-winding transformer, which is suitable in a wide frequency range: from dc up to one decade beyond the maximum working frequency of the transformer.
Abstract: A lumped-component equivalent circuit has been developed by our team to model the electric behavior of any two-winding transformer. This circuit is general: its topology is independent of shape, sizes, and technology chosen. Changing the sample results only in a change of numerical values. Moreover, this circuit is suitable in a wide frequency range: from dc up to, at least, one decade beyond the maximum working frequency of the transformer. The aim of this paper is to present an experimental method which allows all the component values of this equivalent circuit to be determined, using only external impedance measurements. The method is illustrated by one example and, to conclude, Bode plots related to the circuit are compared to the experimental ones. >

93 citations


Patent
18 Aug 1994
TL;DR: In this article, switches are used to set the topology and polarity of a circuit that includes capacitors to deliver an electric pulse to a heart during a defibrillation procedure.
Abstract: The present invention uses switches to set the topology and polarity of a circuit that includes capacitors to deliver an electric pulse to a heart during a defibrillation procedure. The waveform of the electric pulse is biphasic, in that it is a positive portion of the pulse followed by a negative portion of the pulse. The topology and polarity of the circuit are utilized to produce a waveform that approximates the ideal waveform for the specific situation. The circuit provides for combinations of capacitors variously in series and in parallel and changing the topology and polarity of the circuit during discharge of the capacitors.

Journal ArticleDOI
TL;DR: In this article, a general and unified large signal averaged circuit model for current programmed DC-to-DC converters is proposed, from which the large signal characteristics can be derived.
Abstract: A general and unified large signal averaged circuit model for current programmed DC-to-DC converters is proposed. In the averaged circuit model, the active switch is modeled by a current source, with its value equal to the averaged current flowing through it, and the diode is modeled hy the voltage source, with its value equal to the averaged voltage across it. The averaged circuit model has the same topology as the switching converter. The large signal averaged circuit model for current programmed buck, boost, buck-boost and Cuk converters are proposed, from which the large signal characteristics can be obtained. The steady-state and small signal transfer functions of the current programmed DC-to-DC converters can all be derived from their large signal averaged circuit models. The large signal characteristics of the current programmed buck converter are studied by both the phase plane trajectory and the time domain analysis. Experimental prototypes for a current programmed buck converter, with and without an input filter, are breadboarded to verify the analysis. >

Proceedings ArticleDOI
20 Jun 1994
TL;DR: In this paper, a high-quality rectifier employing a coupled-inductor Sepic topology is described, featuring high-frequency insulation and low input current ripple, and sinusoidal and in-phase input current is obtained even with constant duty-cycle.
Abstract: A high-quality rectifier employing a coupled-inductor Sepic topology is described, featuring high-frequency insulation and low input current ripple. Moreover, sinusoidal and in-phase input current is obtained even with constant duty-cycle. The magnetic structure is simple and cheap, allowing considerable size and cost reduction. Converter analysis, design criteria of both power and control sections and experimental results are reported in the paper. >

Patent
23 Nov 1994
TL;DR: In this paper, the authors propose a multi-segment agent topology mechanism for use by multiuser network devices in an Ethernet network, where a device's topology agent maintains and updates topology information in topology tables which identifies interconnected network devices, such as concentrators and bridges, by IP address and segment identifier information.
Abstract: A multi-segment agent topology mechanism for use by multi-segment network devices in an Ethernet network. Topology information packets exchanged between topology agents in a network include segment identifier information as well as IP address of the sending agent. A device's topology agent maintains and updates topology information in topology tables which identifies interconnected network devices, such as concentrators and bridges, by IP address and segment identifier information as well as incoming slot and port information for eventual use by a network management system in evaluating a networks topology map, and in automatically determining changes in the network's topology.

Patent
29 Aug 1994
TL;DR: In this article, a method for determining the topology of a computer network including data-relay devices (A, B, C) and node devices (d,... k) based on a comparison of source addresses heard by the various data relay-devices is presented.
Abstract: An apparatus and method for determining the topology of a computer network including data-relay devices (A, B, C) and node devices (d, ... k) based on a comparison of source addresses heard by the various data relay-devices. A source address table is compiled for each port of each data-relay device, and for each select pair of ports the addresses in the source tables are compared to determine whether there is an intersection of heard devices. In order to account for directed transmissions which are not heard at every port, further comparison is made of all of the other ports of the device, eliminating the ports for which the intersection is the empty set. From the determined connections, a topology of the network is graphed showing direct and transitive connections. In cases where there is both a direct and transitive connection, the redundant direct connection is eliminated.

Journal ArticleDOI
TL;DR: In this article, a three-phase single-switch AC-DC flyback converter system is presented, which operates in the discontinuous mode, and the simple structure of its power and control circuit, low mains current distortion, and resistive fundamental behavior, as well as the high-frequency isolation of the controlled output voltage, have been pointed out.
Abstract: In this paper, a new three-phase single-switch AC-DC flyback converter system is presented. The system operates in the discontinuous mode. The simple structure of its power and control circuit, low mains current distortion, and resistive fundamental behavior, as well as the high-frequency isolation of the controlled output voltage, have to be pointed out. Besides the analysis of the stationary operating behavior, the dependencies of the peak values, average values, and rms values of the device currents, and of the maximum blocking voltages across the power electronic devices on the circuit parameters, are given as analytic approximations. The theoretical analysis is verified by digital simulation. >

Journal ArticleDOI
TL;DR: In this article, a new method for time-domain analysis of power electronics circuits is developed based on the following principles: (a) the switching topology is a linear time-invariant circuit; (b) at each instant, the voltage across a capacitor and the current through an inductor have a certain value, like an independent voltage- or current source, respectively; (c) generally, no switching relationship between the externally and internally controlled switches may be assumed; (d) prior knowledge of the internally controlled switch' operation is not available; and (e) the
Abstract: A new method for time-domain analysis of power electronics circuits is developed based on the following principles: (a) at each instant, the switching topology is a linear time-invariant circuit; (b) at each instant, the voltage across a capacitor and the current through an inductor have a certain value, like an independent voltage- or current source, respectively; (c) generally, no switching relationship between the externally and internally controlled switches may be assumed; (d) prior knowledge of the internally controlled switches' operation is not available; and (e) the switching action may change the response of the circuit immediately after the switching moment, implying that some constraints may be in violation of the presumed switches' states. The algorithm is based on solving a system of algebraical modified nodal equations at each integration step. The number of systems to be solved equals the number of topologies the converter goes through in a cycle. This feature, and the fact that no solutions of time-differential equations or Laplace transform inverses are required, cause the algorithm to be a fast one. At each step, the presumed state of all the switches is checked, and if some constraints are violated, the program looks for another valid topology. An example, with parasitic effects taken into account, is presented; the experimental results, as well as the simulation results obtained by using other available algorithms, confirmed the accuracy of the results achieved with the presented approach. >

01 Jan 1994
TL;DR: In this article, a new topology for multicomputer networks, called recursive circulant, has been proposed, which is defined to be a circuitulant graph with N nodes and jumps of powers of d, d/spl ges/2.
Abstract: We propose a new topology for multicomputer networks, called recursive circulant. Recursive circulant G(N, d) is defined to be a circulant graph with N nodes and jumps of powers of d, d/spl ges/2. G(N, d) is node symmetric, has a hamiltonian cycle unless N/spl les/2, and can be recursively constructed when N=cd/sup m/, 1/spl les/c/spl les/d. We analyze various network metrics of G(cd/sup m/, d) such as connectivity, diameter, mean internode distance, visit ratio, and develop a shortest path routing algorithm in G(cd/sup m/, d). G(2/sup m/, 4), whose degree is m, compares favorably to the hypercube Q/sub m/. G(2/sup m/, 4) has the maximum connectivity, and its diameter is [(3m-1)/4]. A simple broadcasting algorithm in G(2/sup m/, 4) is also presented.<>

Proceedings ArticleDOI
02 Oct 1994
TL;DR: In this article, the average current mode control technique was used to obtain sinusoidal input current in Cuk and Sepic converters in continuous conduction mode, and it was shown that stability can be achieved by using a suitable damping network, which properly shapes the current transfer function without introducing significant power losses.
Abstract: Sepic and Cuk converters used as power factor preregulators in continuous conduction mode are analyzed. The application of the average current mode control technique to obtain sinusoidal input current is investigated. It is shown that, unlike the usual boost topology, the gain of the internal current loop depends strongly on the instantaneous input voltage. Moreover, the presence of undamped complex poles and zeroes makes difficult the design of a stable control. The paper shows that stability can be achieved by using a suitable damping network, which properly shapes the current loop transfer function without introducing significant power losses. With this provision, a standard PI controller can be used to ensure the desired phase margin in any operating condition. Detailed design criteria of both power and control stages are given in the paper. Results of a 300 W prototype based on the Sepic topology are also reported. >

Journal ArticleDOI
TL;DR: In this article, a four-section HBT DA with attenuation compensation on both the input and output transmission lines achieves a gain of 15 dB and a 3-dB bandwidth of >15 GHz.
Abstract: We report on a novel HBT distributed amplifier design which achieves the highest gain-bandwidth product (GBP) per device f/sub T/ so far reported for HBT distributed amplifiers. This paper introduces a new design topology for HBT DA's which incorporates attenuation compensation on both the input and output transmission lines. A four-section HBT DA using this novel topology achieves a gain of 15 dB and a 3-dB bandwidth of >15 GHz. The resulting gain-bandwidth product is 84 GHz. When normalized to the device f/sub T/, this DA achieves the highest normalized gain-bandwidth-product figure of merit for HBT DA's, /spl ap/3.67, which is a 55% improvement over existing state-of-the-art performance. Attenuation compensation of the input transmission line is realized using HBT active impedance transformations. The resulting transistor configuration consists of a common-collector driving a common-emitter-cascode transistor pair. This configuration offers 15-20 dB more available gain for the device unit cell, and results in gain-bandwidth product improvements of 200% over a conventional common-emitter DA configuration. This paper discusses the design theory, techniques, and measurements of this newly developed HBT distributed amplifier topology. >

Proceedings ArticleDOI
13 Feb 1994
TL;DR: In this paper, the authors proposed a forward topology with resonant reset, which combines the simplicity of its power stage with the feasibility to implement self-driven synchronous rectification.
Abstract: The minimization of size and losses are the main goals in the design of high power density and low output voltage onboard DC/DC power converters. Forward topology with resonant reset combines the simplicity of its power stage with the feasibility to implement self driven synchronous rectification. Several operation modes for this topology are proposed and analyzed in this paper: fixed frequency PWM and constant off-time variable frequency, with and without zero voltage switching (ZVS). Design guidelines and experimental results are also provided for 3.3 V output voltage converters, featuring efficiencies up to 90%. >

Journal ArticleDOI
TL;DR: It is suggested that the proposed CS-PPRI is a viable alternative for realizing electronic ballasts for low and high-intensity discharge lamps by having a load independent output current and zero voltage switching (ZVS).
Abstract: A novel topology, current-sourcing push-pull parallel-resonance inverter (CS-PPRI) was investigated theoretically and experimentally. The proposed power stage is built around a current fed push-pull inverter. The main features of the proposed inverter are: a load independent output current and zero voltage switching (ZVS). It is suggested that the proposed CS-PPRI is a viable alternative for realizing electronic ballasts for low and high-intensity discharge lamps. >

Proceedings ArticleDOI
13 Feb 1994
TL;DR: In this article, a buck/boost bidirectional DC/DC converter is proposed using the constant frequency zerovoltage switching (ZVS) multi-resonant topology.
Abstract: A family of bidirectional DC/DC converters is proposed using the constant frequency zero-voltage switching (ZVS) multi-resonant topology. This family of converters provides ZVS operation of all semiconductor devices from no-load to full-load while achieving full DC conversion ratio range, and has inherent short-circuit protection capability. Analysis and design considerations of a buck/boost bidirectional converter are discussed along with experimental results supporting the proposed concept. >

Journal ArticleDOI
Yehuda Afek1
TL;DR: This work addresses the problem of electing a leader in an anonymous, asynchronous network of arbitrary topology with algorithms considerably simpler than known algorithms and have equal or improved communication complexity.
Abstract: We address the problem of electing a leader in an anonymous, asynchronous network of arbitrary topology Our algorithms are considerably simpler than known algorithms and have equal or improved communication complexity

Proceedings ArticleDOI
20 Jun 1994
TL;DR: In this paper, a symmetrical, current-fed DC-DC boost converter was investigated theoretically and experimentally on a 300 W prototype in the frequency range: 40 to 110 kHz, built around an L-type half-bridge IGBT inverter.
Abstract: A symmetrical, current-fed DC-DC boost converter was investigated theoretically and experimentally on a 300 W prototype in the frequency range: 40 to 110 kHz. The converter is built around an L-type half-bridge IGBT inverter. Zero-current-switching is achieved by a series resonant LC-network placed between the collectors of the IGBTs. >

Patent
Norman R. Scheinberg1
27 Sep 1994
TL;DR: In this paper, a monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver, including three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator.
Abstract: A monolithic upconverter integrated circuit is described which performs the first frequency conversion of a dual conversion cable television (CATV) receiver The upconverter chip includes three functional blocks: a Gilbert type image-rejecting mixer, a phase splitter, and a voltage-controlled oscillator Mixing is performed by a novel Gilbert type mixer including image-rejection inductors to improve the noise figure of the mixer A differential circuit topology allows the monolithic upconverter chip to utilize a plastic dual inline batwing package without considerable performance loss On-chip RF bypass networks, in the form of series RC terminations, also help compensate for the undesirable effects of pin inductances in the dual inline package A resistor-based DC biasing scheme dramatically reduces power-up latency, allowing faster testing

Journal ArticleDOI
TL;DR: Some results on certain finite and locally finite spaces which may be used in image processing are reviewed, and algorithms related to these results are given and discussed.
Abstract: Some results on certain finite and locally finite spaces which may be used in image processing are reviewed, and algorithms related to these results are given and discussed.

Journal ArticleDOI
01 Jan 1994
TL;DR: In this article, a switch model based on the associated discrete circuit (ADC) models is proposed, which enables a switching circuit to be modelled by a constant admittance matrix, irrespective of its switching state.
Abstract: The paper describes a new switch model based on the associated discrete circuit (ADC) models. The switch model enables a switching circuit to be modelled by a constant admittance matrix, irrespective of its switching state. This feature allows a system with changing topology to be modelled efficiently and elegantly by one set of model equations, and a reduction of circuit formulation and computing time. The switch model is applied to the simulation of a half-bridge switched-mode circuit. Experimental results confirm the validity of the new switch model.

01 Jan 1994
TL;DR: A new switch model based on the associated discrete circuit (ADC) models enables a switching circuit to be modelled by a constant admittance matrix, irrespective of its switching state, and a reduction of circuit formulation and computing time is described.
Abstract: The paper describes a new switch model based on the associated discrete circuit (ADC) models. The switch model enables a switching circuit to be modelled by a constant admittance matrix, irrespective of its switching state. This feature allows a system with changing topology to be modelled efficiently and elegantly by one set of model equations, and a reduction of circuit formulation and computing time. The switch model is applied to the simulation of a half-bridge switched-mode circuit. Experimental results confirm the validity of the new switch model

Proceedings ArticleDOI
02 Oct 1994
TL;DR: In this article, the authors proposed a passively clamped quasi-resonant DC link power converter topology which adds a small switched inductor to the conventional passive clamped resonant DC-link inverter to solve the problem of high voltage stress in the conventional inverter.
Abstract: This paper proposes a passively clamped quasi-resonant DC link power converter topology which adds a small switched inductor to the conventional passively clamped resonant DC link inverter. The problem with high voltage stress in the conventional inverter is resolved, while its ruggedness, reliability and high power handling capability are preserved. The device voltage stress can be reduced from 2 per unit to 1.1-1.3 per unit, and PWM operation and link resonance control become easily fulfilled. Analysis and simulation have demonstrated the successful operation of the new topology. The introduction of the auxiliary switched inductor circuit is also well justified by its requirement of components with low stresses and ratings. Application of the quasi-resonant inverter is aimed at those requiring high power, high efficiency, low EMI and a high quality spectrum. >