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Showing papers on "Topology (electrical circuits) published in 1998"


Journal ArticleDOI
TL;DR: In this article, the authors describe a rail-to-rail class-AB output stage with folded mesh feedback control that combines power efficiency with operation down to 1.8 V and allows sufficient gain in a compact two-stage topology.
Abstract: Compact low-voltage power-efficient operational amplifiers are described that are very suitable as very-large-scale-integration library cells because of the small die area of 0.08 mm/sup 2/ and the minimum supply voltage of 1.8 V. A key part of the circuit is the rail-to-rail class-AB output stage with folded mesh feedback control that combines power efficiency with operation down to 1.8 V and allows sufficient gain in a compact two-stage topology. A version with rail-to-rail input stage features a rail-to-rail input range for supply voltages down to 2.5 V. The dc gain of the op amps is more than 80 db while driving 10 k/spl Omega/, and the unity-gain frequency is 4 MHz with phase margin of 67/spl deg/ while driving 5 pF. The equivalent input noise voltage is 38 nV//spl radic/(Hz) at a frequency of 100 kHz. The amplifiers have been implemented in a standard digital 1.6-/spl mu/m complementary metal-oxide-semiconductor process.

239 citations


Patent
24 Jun 1998
TL;DR: In this article, a spanning tree support protocol for topology discovery is presented, and a set of states for association with each port of a network device is provided, including a 'blocked' state in which both learning and forwarding remains inhibited, and an 'non-blocked', which allows both forwarding and learning and learning to be allowed.
Abstract: A method and apparatus for providing spanning tree support are provided. According to one aspect of the present invention, a network device includes two or more ports that are a part of a trunk. One of the two or more ports is selected for participation in a loop-free topology discovery protocol (520). Then, the loop-free topology discovery protocol is executed for the selected port (540). If the loop-free topology discovery protocol indicates the selected port is to be blocked (550), then all the ports of the trunk are to be blocked (560). According to another aspect of the present invention, a set of states for association with each port of a network device is provided. The set of states includes a 'blocked' state in which both learning and forwarding remains inhibited, and a 'non-blocked' state in which both learning and forwarding are permitted.

183 citations


Journal ArticleDOI
TL;DR: In this article, a single-phase high-efficiency near-unity power-factor (PF) half-bridge boost converter circuit is presented with detailed analysis and design considerations for the power circuit using the fixed-band hysteresis current control (HCC) technique.
Abstract: A single-phase high-efficiency near-unity power-factor (PF) half-bridge boost converter circuit, which has been proposed earlier by other researchers, is presented with detailed analysis. This converter is capable of operating under variable PF. However, the focus of this paper is in achieving unity PF operation only. The efficiency of this circuit is high because there is only one series semiconductor on-state voltage drop at any instant. The existence of an imbalance in the voltages of the two DC-link capacitors, which was noted before, is confirmed here. The cause for the imbalance is analyzed using appropriate models, and a control method to eliminate it is discussed in detail. Analysis and design considerations for the power circuit using the fixed-band hysteresis current control (HCC) technique are provided. The analytical results are verified through simulation using switched and averaged circuit models of the scheme and also through experimental work. At 90-V AC input and 300-W 300-V output, the experimental prototype demonstrates an efficiency of 96.23% and a PF of 0.998. This converter, with its relatively high DC-output voltage, is well suited for the 110-V utility supply system. A circuit modification for universal input voltage range operation is also suggested.

174 citations


Proceedings ArticleDOI
14 May 1998
TL;DR: This pciper summarizes the state of the art in this rapidly developing field of power electronics with swirching converters to medium voltage applications.
Abstract: Multilevel power converters represent a potential breakthrou,qh in employing swirching converters to medium voltage applications (2-13 k w . This pciper summarizes the stat e of the art in this rapidly a'eveloping Jeld ofpower electronics.

169 citations


Proceedings ArticleDOI
15 Feb 1998
TL;DR: In this paper, a passive power-factor correction circuit was proposed to ensure compliance of the capacitively filtered single-phase rectifier with the EN61000-3-2 norm at a cost much lower than the known solutions.
Abstract: This paper describes a novel passive power-factor correction circuit that ensures the compliance of the capacitively filtered single-phase rectifier with the EN61000-3-2 norm at a cost much lower than the known solutions The circuit can be used to about 300 W The additional components are a small inductor, a small capacitor and a diode

145 citations


Journal ArticleDOI
TL;DR: In this paper, a method for topology error identification based on the use of normalized Lagrange multipliers is proposed, which models circuit breakers as network switching branches whose statuses are treated as operational constraints in the state estimation problem.
Abstract: This paper introduces a method for topology error identification based on the use of normalized Lagrange multipliers. The proposed methodology models circuit breakers as network switching branches whose statuses are treated as operational constraints in the state estimation problem. The corresponding Lagrange multipliers are then normalized and used as a tool for topology error identification, in the same fashion as measurement normalized residuals are conventionally employed for analog bad data processing. Results of tests performed with the proposed algorithm for different types of topology errors are reported.

140 citations


Journal ArticleDOI
TL;DR: A new method for fitting planar structures to the measured sets of point clouds using a semi-automated topology generator for 3-D objects, CC-Modeler (CyberCity Modeler).
Abstract: In this paper, we introduce a semi-automated topology generator for 3-D objects, CC-Modeler (CyberCity Modeler). Given the data as point clouds measured on Analytical Plotters or Digital Stations, we present a new method for fitting planar structures to the measured sets of point clouds. While this topology generator has been originally designed to model buildings, it can also be used for other objects, which may be approximated by polyhedron surfaces. We have used it so far for roads, rivers, parking lots, ships, etc. The CC-Modeler is a generic topology generator. The problem of fitting planar faces to point clouds is treated as a Consistent Labelling problem, which is solved by probabilistic relaxation. Once the faces are defined and the related points are determined, we apply a simultaneous least-squares adjustment in order to fit the faces jointly to the given measurements in an optimal way. We first present the processing flow of the CC-Modeler. Then, the algorithm of structuring the 3-D point data is outlined. Finally, we show the results of several data sets that have been produced with the CC-Modeler.

138 citations


Book ChapterDOI
23 Sep 1998
TL;DR: Initial results of the system as applied to two analog filter design problems suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation.
Abstract: We present a method of evolving analog electronic circuits using a linear representation and a simple unfolding technique. While this representation excludes a large number of circuit topologies, it is capable of constructing many of the useful topologies seen in hand-designed circuits. Our system allows circuit size, circuit topology, and device values to be evolved. Using a parallel genetic algorithm we present initial results of our system as applied to two analog filter design problems. The modest computational requirements of our system suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation.

122 citations


01 Jan 1998
TL;DR: A new PWM inverter topology suitable for medium voltage (2300/4160 V) adjustable speed drive (ASD) systems is proposed, derived by combining three standard 3-phase inverter modules and a 0.33 pu output transformer.
Abstract: In this paper a new PWM inverter topology suitable for medium voltage (2300/4160 V) adjustable speed drive (ASD) systems is proposed. The modular inverter topology is derived by combining three standard 3-phase inverter modules and a 0.33 pu output transformer. The output voltage is high quality, multistep PWM with low dv/dt. Further, the approach also guarantees balanced operation and 100% utilization of each 3-phase inverter module over the entire speed range. These features enable the proposed topology to be suitable for powering constant torque as well as variable torque type loads. Clean power utility interface of the proposed inverter system can be achieved via an 18-pulse input transformer. Analysis, simulation, and experimental results are shown to validate the concepts.

120 citations


Proceedings ArticleDOI
07 Jun 1998
TL;DR: In this article, a synthesis procedure for multiple coupled resonator filters with general topology and general response is described, where the optimization is performed directly on the element values of the coupling matrix.
Abstract: A synthesis procedure, using optimization, for multiple coupled resonator filters having general topology and general response is described. The error function for the optimization is based on the values of the characteristic function at its zeros and poles. The optimization is performed directly on the element values of the coupling matrix. Convergence of the optimization is extremely fast and nearly independent of the starting coupling matrix. Examples of the design of practical filters with symmetric or asymmetric responses and topology are presented.

105 citations


Patent
27 Oct 1998
TL;DR: A pulse width modulation (PWM) controller suitable for use with a variety of open loop topology power supply circuits including ring generator circuits is presented in this paper.The PWM controller is adapted to provide the required signals to control the various possible open loop converter topologies.
Abstract: A pulse width modulation (PWM) controller suitable for use with a variety of open loop topology power supply circuits including ring generator circuits. The controller and the circuit realized therefrom utilizes an open loop topology to achieve the desired output voltage waveform. The PWM controller is suitable for realizing a plurality of different open loop converter topologies such as such as buck, boost, forward and push-pull topologies. The PWM controller is adapted to provide the required signals to control the various possible open loop converter topologies. The controller functions to generate a PWM signal that is used to generate a half wave sine wave signal. The controller includes the necessary functionality to control the duty cycle of the generated PWM signal so as to produce a full wave sine wave at the output of the output bridge circuit.

Proceedings ArticleDOI
21 Sep 1998
TL;DR: In this paper, a new improved boost topology is proposed to reduce the input current ripple, which is realized by adding an extra LC circuit with coupled inductors to the conventional topology.
Abstract: A new improved boost topology is proposed to reduce the input current ripple. The new topology is realized by adding an extra LC circuit with coupled inductors to the conventional boost topology. The operating principle and the small-signal characteristics are analyzed. Comparisons are made between the proposed improved topology and the conventional boost topology. An experimental converter has been built and tested to verify the theoretical analysis.

Proceedings ArticleDOI
14 May 1998
TL;DR: In this article, a set of single positive-type second generation current conveyor based all-pass filters is presented and a catalogue of canonical topologies is given with some properties in tabular form.
Abstract: Current conveyors are unity gain active elements exhibiting high linearity, wide dynamic range and better high frequency performance compared with their voltage mode counterparts. In this study a set of single positive-type second generation current conveyor based all-pass filters is presented and a catalogue of canonical topologies is given with some properties in tabular form. In contrast with single topology presentations, 22 different topologies are presented which exhibit identical transfer functions but differ in the number of passive components, component matching constraints, possibility of gain adjustment and other properties.

Patent
04 Dec 1998
TL;DR: In this article, the authors describe a method for representing devices on a computer network using a topology service, which is capable of sending an alarm notification regarding a device having an associated topology object stored in the database, extracting the topology objects, and acting on said topological object, and propagating the alarm notice to other topology nodes associated with the topological objects; store information related to the alarm and the database; and notifying other services on the computer network.
Abstract: Software, method, and systems for representing devices on a computer network are described. In one embodiment the invention comprises a method which identifies devices on a computer network; creates topology objects configured to represent the devices; associates the topology objects with the identified devices; stores the associated topology objects in a database managed by a topology service. The embodiment further is capable of receiving an alarm notification regarding a device having an associated topology object stored in the database, extracting the topology object, and acting on said topology object update an alarm count in the topology object; propagate the alarm notice to other topology nodes associated with the topology object; store information related to the alarm and the database; and notifying other services on the computer network. Other embodiments update the relationships between the devices and associated topology objects stored in the database.

Journal ArticleDOI
TL;DR: In this article, a double power converter with fully independent regulated outputs is introduced, which results from magnetic integration of flyback and forward power converters, and the derived converter shares a single power switch having a single magnetic component.
Abstract: A double power converter with fully independent regulated outputs is introduced. The proposed topology results from magnetic integration of flyback and forward power converters. The derived converter shares a single power switch having a single magnetic component. Also, only one standard pulsewidth modulation (PWM) integrated modulator is needed in order to keep independent closed-loop control of both output voltages. The double regulation may be sustained over a wide spread of current loads. Boundaries of full regulation and experimental results are presented.

Proceedings ArticleDOI
15 Feb 1998
TL;DR: In this paper, a new circuit for AC-to-AC power conversion is presented, derived from the matrix converter topology, which has the capability of direct AC to AC power conversion without any DC link reactive component and input inductance except a small snubber.
Abstract: In this paper, a new circuit for AC to AC power conversion is presented. The circuit is derived from the matrix converter topology, which has the capability of direct AC to AC power conversion without any DC link reactive component and input inductance except a small snubber. It consists of only unidirectional switches such as IGBTs with antiparallel diodes in contrast to the matrix power converter which consists of bi-directional switches. The input displacement power factor of the proposed scheme is unity and the overall power factor is near unity. The waveform of the input line currents is much alike with the diode a large DC-link reactor. The validity of the circuit and its operation is confirmed by experiments which uses a dynamic load-field oriented induction motor drive system.

Proceedings ArticleDOI
07 Sep 1998
TL;DR: The architecture is based on a gyrator-C topology, where tuneable compensation techniques are applied to reduce phase error due to additional device parasitics, thus extending the useable frequency range of the inductor closer to the f/sub t/ of the technology.
Abstract: This paper presents the design of a differential CMOS active inductor for use in applications around 1-1.7 GHz. The architecture is based on a gyrator-C topology, where tuneable compensation techniques are applied to reduce phase error due to additional device parasitics, thus extending the useable frequency range of the inductor closer to the f/sub t/ of the technology. The inductance value and quality factor are also independently tuneable, and simulation results using device parameters from the AMS 0.8 /spl mu/m CMOS process demonstrate operation at 1.5 GHz with a Q of over 300. The implementation of a tuneable bandpass filter using the inductor is also demonstrated.

Proceedings Article
01 Jan 1998
TL;DR: Topology as well as the parameters of the lumped element equivalent circuit are generated by the method and the applicability of the generated circuit model in transient SPICE simulations could be demonstrated.
Abstract: We present a general method for the generation of lumped element equivalent circuits for linear passive reciprocal distributed microwave components from time domain scattering signals. The method is based on a field theoretical analysis of the distributed multiport circuit in time domain. For this purpose the three-dimensional transmission-line-matrix method is used. A canonical representation of the multiport admittance matrix Y(p) allows one to extract an equivalent circuit directly after specifying the frequency range of validity. Topology as well as the parameters of the lumped element equivalent circuit are generated by the method. A distributed three-port microwave circuit was modeled and the applicability of the generated circuit model in transient SPICE simulations could be demonstrated.

Journal ArticleDOI
TL;DR: In this paper, the authors propose the use of passivation techniques to design power system stabilizers for the synchronous generators and characterize, in terms of a simple linear matrix inequality, a class of linear statefeedback controllers which achieve this objective.

Journal ArticleDOI
TL;DR: In this article, the authors considered the mathematical properties of discrete or discretized mechanical structures under multiple loadings which are optimal w.r.t. maximal stiffness, i.e., minimizing the maximal sum of displacements along an applied force.
Abstract: This paper considers the mathematical properties of discrete or discretized mechanical structures under multiple loadings which are optimal w.r.t. maximal stiffness. We state a topology and/or sizing problem of maximum stiffness design in terms of element volumes and displacements. Multiple loads are handled by minimizing the maximum of compliance of all load cases, i.e., minimizing the maximal sum of displacements along an applied force. Generally, the problem considered may contain constraints on the design variables. This optimization problem is first reformulated in terms of only design variables. Elastic equilibrium is hidden in potential energy terms. It is shown that this transformed objective function is convex and continuous, including infinite values. We deduce that maximum stiffness structures are dependent continuously on the bounds of the element volumes as parameters. Consequently, solutions to sizing problems with small positive lower bounds on the design variables can be considered as good approximations of solutions to topology problems with zero lower bounds. This justifies heuristic approaches such as the well-known stress-rationing method for solving truss topology problems.

Journal ArticleDOI
TL;DR: In this article, a zero-voltage-transition (ZVT) pulse-width-modulation (PWM) multiphase converters are presented, where only one auxiliary circuit provides the zerovoltage switching (ZVS) for main switches and diodes of all phases.
Abstract: Novel zero-voltage-transition (ZVT) pulse-width-modulation (PWM) multiphase converters are presented. To construct a ZVT multiphase converter in a conventional way, it is necessary to add the auxiliary circuits with as many number of phases. In the proposed converter, only one auxiliary circuit provides the zero-voltage switching (ZVS) for main switches and diodes of all phases. So, the new converters are cost effective and attractive for high-performance and high power-density conversion applications. Operation, features, and characteristics of the two-phase buck converter are illustrated and verified on a 4-kW 100-kHz insulated gate bipolar transistor (IGBT)-based (a MOSFET for the auxiliary switch) experimental circuit.

Journal ArticleDOI
TL;DR: In this paper, a permanent magnet (PM) motor based on the slotless axial-flux permanent magnet machine (AFPM) topology can be used to advantageously compete with the induction motor for low-cost drive application.
Abstract: The variable-speed driven pump can result in significant energy conservation where reduced flow rates are required for long periods of time. In regard to adjustable-speed pump drives, one major contribution of this paper is the demonstration that a permanent magnet (PM) motor based on the slotless axial-flux permanent magnet machine (AFPM) topology can be a suitable candidate to advantageously compete with the induction motor for such a low-cost drive application. For the purpose of a cost comparison, the paper discusses design and construction of a prototype machine which has been conceived to replace a 1.2 HP induction motor being used in a standard adjustable-speed pump drive. Results taken from laboratory tests of the prototype machine are reported, together with an assessment of the machine manufacturing cost.

Proceedings ArticleDOI
T. Yamane1, S. Hamamura, T. Zaitsu2, T. Minomiya1, Masahito Shoyama1, Y. Fuda 
17 May 1998
TL;DR: In this article, the improvement of the converter efficiency by using a different rectifier circuit topology and a synchronous-rectifier technique is described, and the frequency characteristics of efficiency are improved by using different topology of the input filter circuit and its optimum design.
Abstract: Piezoelectric-transformers (PT) have a lot of merits in comparison with magnetic transformers. We have previously presented some types of piezoelectric-transformer DC-DC converters (PT-converters) for AC-adapters, but their efficiency was restricted. The maximum efficiency was less than 80%. Furthermore, the frequency characteristics of efficiency are not good due to the power loss generated in the input filter circuit of the PT. In this paper the improvement of the converter efficiency by using a different rectifier circuit topology and a synchronous-rectifier technique is described. Furthermore, the frequency characteristics of efficiency are improved by using a different topology of the input filter circuit and its optimum design. As a result, the converter efficiency has been increased up to 88% and the frequency characteristics of the efficiency is also improved.

Journal ArticleDOI
TL;DR: In this paper, an integrated RF circuit topology that can be used to realize low voltage (i.e., 1 V) RF integrated circuits is presented. But, the low-voltage version has a similar distortion specification as the classic 2 V low-noise cascode amplifier and a 0.22 dB improvement in noise figure.
Abstract: We report an integrated RF circuit topology that can be used to realize low voltage (i.e., 1 V) RF integrated circuits. The scheme uses on-chip capacitively coupled resonating elements to DC isolate circuit elements that under the present art are connected in series and share a common DC current. The topology is applied to several commonly used RF integrated circuit topologies (i.e., low-noise amplifiers and mixers). A comparison is made between a low-voltage version of a cascode amplifier and the classic cascode amplifier. The low-voltage version (i.e., 1 V) is shown to have a similar distortion specification as the classic 2 V low-noise cascode amplifier. The low-voltage version has a 0.22 dB improvement in noise figure.

Journal ArticleDOI
TL;DR: A new quasi-parallel resonant DC-link inverter with the more flexible pulse-width-modulation (PWM) capability and easier control is proposed in this paper with the addition of one coupling core and one diode.
Abstract: A new quasi-parallel resonant DC-link inverter with the more flexible pulse-width-modulation (PWM) capability and easier control is proposed in this paper. With the addition of one coupling core and one diode, the circuit can be directly applied to the single/three-phase inverter to achieve the soft-switching action. For the proposed topology, it needs neither the help of the inverter switch devices nor the requirement of voltage/current sensors. Random duration of the zero DC-link voltage can be obtained, and the voltage stresses of the inverter switches can be maintained to the minimum. The relative analysis of the presented circuit has been performed and verified by the experiment.

Journal ArticleDOI
17 May 1998
TL;DR: In this article, a modified asymmetrical pulsewidth-modulated resonant dc/dc converter employing an auxiliary circuit consists of a network of two capacitors and an inductor.
Abstract: A modified asymmetrical pulse-width-modulated resonant dc/dc converter employing an auxiliary circuit will be proposed in this paper. The auxiliary circuit consists of a network of two capacitors and an inductor. The aim of this network is to produce zero-voltage-switching (ZVS) over a wide input voltage range, while reducing the voltage stress on the resonant component. A detailed analysis and performance characteristics are presented. Experimental results for a 5 V, 35 W converter show an efficiency of 83% at a constant operating frequency of 500 kHz. Using metal oxide semiconductor field effect transistors (MOSFETs) as synchronous rectifiers can further reduce power losses and improve the efficiency to be greater than 90%.

Patent
30 Apr 1998
TL;DR: The virtual-chassis topology as mentioned in this paper relies on an asymmetrical trunk mode in which each front-plane switch is operating in trunk mode, while the back-plane switches are not.
Abstract: A “virtual-chassis” topology network includes three or more “front-plane” switches and two or more “back-plane switches”. Front-plane switches can be added to increase the number of ports available for connecting network segments; port count can be exchanged for bandwidth by adding more back-plane switches. The virtual-chassis topology relies on an asymmetrical trunk mode in which each front-plane switch is operating in trunk mode, while the back-plane switches are not. The number of ports per trunk equals the number of back-plane switches so that each front-plane switch is coupled to every back-plane switch (and vice versa). Each back-plane switch is only coupled to front-plane switches, while the untrunked ports of front-plane switches are available for links to network segments. In this topology, every node device (belonging to a segment connected to a front-plane port) is separated by at most three switches from any other node device (also belonging to a segment connected to a front-plane port). The topology is fault-tolerant in that, if any link between the front plane and the back plane is broken, or if an entire back-plane switch fails, the network can reroute packets to avoid the broken link or links. Without impairing performance, the topology can be expanded so that the number of ports available to network segments is almost the square of the number of ports per front-plane switch. The availability of the virtual-chassis topology allows a network user to acquire even a single switch with the confidence that it will remain useful as the network expands.

Proceedings ArticleDOI
29 Mar 1998
TL;DR: This work addresses the problem of estimating the spectrum required in a wireless network for a given demand and interference pattern, and designs efficient algorithms that exploit the geometric structure of the hexagonal grid topology to determine upper bounds on the spectrum requirement for arbitrary demand patterns.
Abstract: We address the problem of estimating the spectrum required in a wireless network for a given demand and interference pattern. This problem can be abstracted as a generalization of the graph coloring problem, which typically presents additional degree of hardness compared to the standard coloring problem. It is worthwhile to note that the question of estimating the spectrum requirement differs markedly from that of allocating channels. The main focus of this work is to obtain strong upper and lower bounds on the spectrum requirement, as opposed to the study of spectrum allocation/management. While the relation to graph coloring establishes the intractability of the spectrum estimation problem for arbitrary network topologies, useful bounds and algorithms are obtainable for specific topologies. We establish some new results regarding generalized coloring, which we use to derive tight bounds for specific families of graphs. We also examine the hexagonal grid topology, a commonly used topology for wireless networks. We design efficient algorithms that exploit the geometric structure of the hexagonal grid topology to determine upper bounds on the spectrum requirement for arbitrary demand patterns. The slack in our upper bounds is estimated by analyzing subgraphs with specific properties. While we consider the worst-case demand patterns to evaluate the performance of our algorithms, we expect them to perform much better in practice.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the general performance criteria and the speed/dynamic range limits of current-mode G/sub m/-C based filters, compared to conventional voltage-mode filters, provided that both kinds of filter topology employ the same type of transconductors and capacitors.
Abstract: As there is a growing interest in the design of so called "current-mode filters", this paper is concerned with an investigation into the general performance criteria and the speed/dynamic range limits of current-mode G/sub m/-C based filters, compared to conventional voltage-mode G/sub m/-C filters. It is shown here that, as far as speed, dynamic range, and power consumption are concerned and provided that both kinds of filter topology employ the same type of transconductors and capacitors, the result comes out in the favor of the use of the voltage-mode filter processing as a solution for realizing high performance G/sub m/-C filters.

Patent
Yuval Shavitt1
21 Sep 1998
TL;DR: In this paper, a spanning tree aggregation topology is proposed to reduce a full-mesh topology from an original sub-network topology to a first spanning tree topology.
Abstract: Efficient topology aggregation is realized by generating a full-mesh topology from an original sub-network topology, without compromising accuracy. Then, the full-mesh topology is reduced to a first spanning tree aggregation topology. Distortion in the first spanning tree aggregation topology is evaluated to determine if the resultant spanning tree aggregation topology requires further refinement in order to meet a predetermined distortion criterion. If no further refinement is required, the aggregation topology is advertised. Additionally, a network parameter, e.g., a so-called network radius is generated from the full-mesh topology. In this example, the network parameter is evaluated along with the first spanning tree aggregation topology to determine if the spanning tree aggregation topology requires further refinement. If no further refinement is required, both the aggregation topology and the network parameter are advertised.