Showing papers on "Topology (electrical circuits) published in 2000"

Topology control of multihop wireless networks using transmit power adjustment

Abstract: We consider the problem of adjusting the transmit powers of nodes in a multihop wireless network (also called an ad hoc network) to create a desired topology. We formulate it as a constrained optimization problem with two constraints-connectivity and biconnectivity, and one optimization objective-maximum power used. We present two centralized algorithms for use in static networks, and prove their optimality. For mobile networks, we present two distributed heuristics that adaptively adjust node transmit powers in response to topological changes and attempt to maintain a connected topology using minimum power. We analyze the throughput, delay, and power consumption of our algorithms using a prototype software implementation, an emulation of a power-controllable radio, and a detailed channel model. Our results show that the performance of multihop wireless networks in practice can be substantially increased with topology control.

A generalized multilevel inverter topology with self voltage balancing

Abstract: Multilevel power converters that provide more than two levels of voltage to achieve smoother and less distorted AC-to-DC, DC-to-AC, and DC-to-DC power conversion, have attracted many contributors. This paper presents a generalized multilevel inverter (converter) topology with self voltage balancing. The existing multilevel inverters such as diode-clamped and capacitor-clamped multilevel inverters can be derived from the generalized inverter topology. Moreover, the generalized multilevel inverter topology provides a true multilevel structure that can balance each DC voltage level automatically without any assistance from other circuits, thus, in principle, providing a complete and true multilevel topology that embraces the existing multilevel inverters. From this generalized multilevel inverter topology, several new multilevel inverter structures can be derived. Some application examples of the generalized multilevel converter are given.

Improved sense-amplifier-based flip-flop: design and measurements

Abstract: Design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented. It was found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage. The new flip-flop uses a new output stage latch topology that significantly reduces delay and improves driving capability. The performance of this flip-flop is verified by measurements on a test chip implemented in 0.18 /spl mu/m effective channel length CMOS. Demonstrated speed places it among the fastest flip-flops used in the state-of-the-art processors. Measurement techniques employed in this work as well as the measurement set-up are discussed in this paper.

Generating network topologies that obey power laws

Abstract: Recent studies have shown that Internet graphs and other network systems follow power-laws. Are these laws obeyed by the artificial network topologies used in network simulations? Does it matter? In this paper we show that current topology generators do not obey all of the power-laws, and we present two new topology generators that do. We also re-evaluate a multicast study to show the impact of using power-law topologies.

Protection cycles in mesh WDM networks

Abstract: A fault recovery system that is fast and reliable is essential to today's networks, as it can be used to minimize the impact of the fault on the operation of the network and the services it provides. This paper proposes a methodology for performing automatic protection switching (APS) in optical networks with arbitrary mesh topologies in order to protect the network from fiber link failures. All fiber links interconnecting the optical switches are assumed to be bidirectional. In the scenario considered, the layout of the protection fibers and the setup of the protection switches is implemented in nonreal time, during the setup of the network. When a fiber link fails, the connections that use that link are automatically restored and their signals are routed to their original destination using the protection fibers and protection switches. The protection process proposed is fast, distributed, and autonomous. It restores the network in real time, without relying on a central manager or a centralized database. It is also independent of the topology and the connection state of the network at the time of the failure.

A novel integrated current doubler rectifier

Abstract: This paper presents an innovative current doubler rectifier, which integrates all the magnetic components into a single core and minimizes the number of high current windings. Compared to the conventional approach, the proposed integrated magnetic structure features reduced core loss, smaller core size, and reduced AC conduction losses, all while still reducing winding losses. The new rectification circuit can be applied to many topologies. An asymmetrical half-bridge converter was used as one attractive example to demonstrate the operation and performance of the proposed structure. A prototype featuring 400 V input, 48 V output, 200 kHz switching frequency, and 1 kW output power was also developed based on this topology.

Topology of the fittest transportation network.

Abstract: The presence or absence of loops in the emergent transportation networks, that are characterized by a minimum overall cost, is shown to depend on the convexity of the cost function for the local transportation of material. Our results are directly applicable to a variety of situations across disciplines.

Topology optimization of compliant mechanical amplifiers for piezoelectric actuators

Abstract: A method for the design of displacement amplifying compliant mechanisms for piezoelectric actuators is developed using a topology optimization approach. The overall stroke amplification or geometric advantage of the mechanism, and the overall mechanical efficiency of the mechanism are considered as objective functions. The maximization of these objective functions is accomplished using two different solution methods, Sequential Linear Programming and an Optimality Criteria method. The focus of this paper is on the underlying topology optimization problem formulations and the solution methods. Design examples are presented which illustrate the method, with comparisons of the computation time and mechanism performance for the two formulations and solution methods. A procedure has also been developed to automatically convert the topology optimization results to a solid CAD model. A prototype design has been fabricated to serve as proof of concept.

Corrections to "accurate circuit model of interdigital capacitor and its application to design of new quasi-lumped miniaturized filters with suppression of harmonic resonance"

Abstract: A general-purpose circuit model of a microstrip interdigital capacitor (IDC) is presented in this paper for use in the design of new quasi-lumped miniaturized filters. This computer-aided-design-oriented model is developed as a versatile admittance /spl pi/-network with the short-open calibration technique that we have recently proposed for accurate parameter extraction of a circuit from its physical layout. This technique is self-contained in our method of moments, which accounts for frequency dispersion and fringing effects. A J-inverter topology is further conceived to explicitly formulate the coupling behavior of three types of IDC's. This model provides a unique way for the IDC-related circuit synthesis and optimization based on the accurate equivalent-circuit network extracted from the field theory algorithm. It is validated theoretically and experimentally through an example of a line resonator connected with two IDC's. The proposed scheme is used in the design and optimization of new low-loss miniaturized quasilumped integrated circuits, namely, two types of three-pole direct-coupled bandpass filters. Our measured and predicted results show interesting features of the proposed filter structure such as size reduction and suppression of harmonic resonance if the line resonator is attached by series-connected equivalent inductance.

Method and system for identifying and processing changes to a network topology

Abstract: A method and system are disclosed for mapping the topology of a network having interconnected nodes by identifying changes in the network and updating a stored network topology based on the changes. The nodal connections are represented by data tuples that store information such as a host identifier, a connector interface, and a port specification for each connection. A topology database stores an existing topology of a network. A topology converter accesses the topology database and converts the existing topology into a list of current tuples. A connection calculator calculates tuples to represent connections in the new topology. The topology converter receives the new tuples, identifies changes to the topology, and updates the topology database using the new tuples. The topology converter identifies duplicate tuples that appear in both the new tuples and the existing tuples and marks the duplicate tuples to reflect that no change has occurred to these connections. The topology converter attempts to resolve swapped port conditions and searches for new singly-heard and multi-heard host link tuples in the list of existing tuples. The topology converter also searches for new conflict link tuples in the existing tuples. The topology converter updates the topology database with the new topology.

A new matrix converter-motor (MCM) for industry applications

Abstract: The trend in electrical drives is to integrate the frequency converter, the electrical motor and even the gear or the pump into a single unit, in order to reduce the costs and to increase the overall efficiency and the equipment reliability This paper presents the first integrated regenerative frequency converter-motor for industry applications, based on a matrix converter topology The low volume, the sinusoidal input current, the bi-directional power flow and the lack of the bulky and limited-lifetime electrolytic capacitors recommend this topology for this application This paper shows how the matrix converter disadvantages-the lack of bi-directional power devices, the lower voltage transfer ratio, the lack of ride-through capability and the overvoltages caused by the input filter during power-up-which have delayed the industrial implementation, have been overcome In order to demonstrate the validity of the solution, a 4 kW matrix converter-motor (MCM) prototype is built using a standard frequency converter-motor enclosure and tested to meet the requirements for an industrial drive

Modeling and nonlinear control of shunt active power filter in the synchronous reference frame

Abstract: This paper presents a modeling and a nonlinear control of three-phase voltage source shunt active filter. The modeling is based on the abc/dq transformation of the AC system variables. The currents injected by the active filter are controlled in the synchronous orthogonal dq frame using a decoupled nonlinear control strategy. The reference harmonic components are extracted from the sensed nonlinear load currents by applying the synchronous reference frame method, where a three-phase thyristor bridge rectifier with R-L load is taken as the nonlinear load. The voltage level of the DC side is regulated using a linearizing feedback control. The reference current needed to maintain a regulated DC voltage is added to the current loop reference. The transfer functions of the two loops are developed and synthesized to obtain the desired stability and dynamic response. Simulation results confirm the performances considered theoretically for the shunt active filter topology.

Virtual topology reconfiguration of wavelength-routed optical WDM networks

Abstract: The bandwidth requirements of the Internet are increasing every day and there are newer and more bandwidth-thirsty applications emerging on the horizon. Wavelength division multiplexing (WDM) is the next step towards leveraging the capabilities of the optical fiber, especially for wide-area backbone networks. The ability to switch a signal at intermediate nodes in a WDM network based on their wavelengths is known as wavelength-routing. One of the greatest advantages of using wavelength-routing WDM is the ability to create a virtual topology different from the physical topology of the underlying network. This virtual topology can be reconfigured when necessary, to improve performance. We discuss the previous work done on virtual topology design and also discuss and propose different reconfiguration algorithms applicable under different scenarios.

Conducted EMI issues in a 600-W single-phase boost PFC design

Abstract: This paper presents the results of experimental activity concerned with the development of a 600 W boost power-factor corrector (PFC) complying with the EMC standards for conducted EMI in the 150 kHz 30 MHz range. In order to accomplish this task, different circuit design and layout solutions are taken into account and their effect on the conducted EMI behavior of the converter is experimentally evaluated. Common-mode and differential-mode switching noise, together with input filters' design and topology and with the printed circuit board layout (in terms of track length and spacing, ground and shielding planes, etc.) are the key aspects which have been considered. In particular, the paper reports the conducted EMI measurements for different filter capacitor placements and values, for different power switch drive circuits, together with several other provisions which have turned out to be decisive in the reduction of the generated EMI.

Virtual L2TP/VPN tunnel network and spanning tree-based method for discovery of L2TP/VPN tunnels and other layer-2 services

Abstract: A virtual L 2 TP/VPN tunnel network as well as a system and method for automatic discovery of VPN tunnels, such as L 2 TP tunnels, and other layer- 2 services using a method such as one based on the spanning tree protocol are disclosed. The method for automatic discovery of layer- 2 services across a network of layer- 2 devices generally comprises transmitting an advertisement message on each tunnel of each layer- 2 device, the advertisement message containing information for generating a spanning tree based on spanning tree algorithm, receiving advertisement message on the tunnels of each layer- 2 device, and processing the received advertisement messages to generate a spanning tree topology of the network of layer- 2 devices whereby each layer- 2 device in the network automatically discovers layer- 2 services of other layer- 2 devices on the network. The transmitting is preferably repeated at predetermined configurable intervals.

Design, implementation, and experimental results of bi-directional full-bridge DC/DC converter with unified soft-switching scheme and soft-starting capability

Abstract: The PWM control, design and implementation issues of the bi-directional dual full-bridge DC/DC converter with a unified soft-switching scheme and soft-start capability, which was proposed in a companion paper, are presented in this part of the two-paper sequel. Test results on a 5 kW prototype converter, which is connected between a 12 V battery and a high voltage bus, and targeted for alternative energy applications, validate the secure operation, high reliability and superior efficiency of the proposed converter topology.

Automatic completion and evaluation of road networks

Abstract: Road networks automatically extracted from digital imagery are in general incomplete and fragmented. Completeness and topology of the extracted network can be improved by the use of the global network structure which is a result of the function of roads as part of the transport network. This is especially – but not exclusively – important for the extraction of roads from imagery with low resolution (e.g., ground pixel size 1 m) because only little local evidence for roads can be extracted from those images. In this paper, an approach is described for the completion of incompletely extracted road networks. The completion is done by generating link hypotheses between points on the network which are likely to be connected based on the network characteristics. The proposed link hypotheses are verified based on the image data. A quantitative evaluation of the achieved improvements is given. New developments presented in this paper are the generation of link hypotheses between different connected components of the extracted road network and the introduction of measures for the evaluation of the network topology and connectivity. Results of the improved completion scheme are presented and evaluated based on the introduced measures. The results show the feasibility of the presented completion approach as well as its limitations. Major advantages of the completion of road networks are the improved network topology and connectivity of the extraction result. The new measures prove to be very useful for the evaluation of network topology and connectivity.

Energy storage system using a series connection of supercapacitors, with an active device for equalizing the voltages

Abstract: An energy storage system based on battery and supercapacitors is presented. It allows bigger amount of intantaneous power. The properties of the proposed system are oriented in high efficiency, in a special topology with parallel channels. The paper presents also an active sharing device, for equalizing the voltages across a series connection of supercapacitor. Based on a buck-boost topology, this device ensures an optimal value for the stored energy, with a high equalizingciency.

Fast analysis and optimization of power/ground networks

Abstract: This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes (which are hard to analyze efficiently), and tree-structured networks (which provide poor performance). As an example, we consider a P/G network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. A fast and efficient event-driven P/G network simulator is proposed, which hierarchically simulates the P/G network with an adaptation of PRIMA to handle non-zero initial conditions. An adjoint network that incorporates the variable topology of the original P/G network, as elements switch in and out of the network, is constructed to calculate the transient adjoint sensitivity over multiple intervals. The gradients of the most critical node with respect to each wire width and decap are used by a sensitivity-based heuristic optimizer that minimizes a weighted sum of the wire and the decap area. Experimental results show that this procedure can be used to efficiently optimize large networks.

A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters

Abstract: A new fully differential CMOS dynamic comparator topology suitable for pipeline A/D converters with a low stage resolution is proposed. A thorough analysis of its function and a comparison to a widely used dynamic comparator are given in this paper. The proposed topology, based on two cross coupled differential pairs and switchable current sources, has a small power and area dissipation and it is shown to be very robust against transistor mismatch.

Current-Mode High Output Impedance Sinusoidal Oscillator Configuration Employing Single FTFN

Abstract: In this study, a general current-mode high output impedance sinusoidal oscillator configuration is proposed. The proposed oscillator configuration uses a single four terminal floating nullor (FTFN), two capacitors and five resistors. The oscillator configuration exhibits high output impedance which makes easy to drive loads without using any buffering devices and provide non-interactive control of oscillation condition and oscillation frequency. The proposed topology also yields single frequency oscillators with reduced number of passive components. All of the proposed oscillators permit good frequency stability and exhibit low active and passive sensitivities. Theoretical analysis is verified with experimental results.

Routing switch automatically identifying network topology

Abstract: An automatic network topology identification technique is described herein. Each node in the network periodically or constantly transmits its unique address to its neighboring node. Once a node receives a different message from its neighbor, the node identifies a topology change in the network. In one embodiment, a current topology is associated with a session number. When a change in the topology is detected, the detecting node increments the session number and broadcasts the change in topology. The other nodes, detecting the changed session number, now know that there has been a change in the network. In response, the nodes in the network modify routing tables and other information stored at the node related to the topology. In one embodiment, the technique is used to reassign shortened addresses to each device on the network to support a dual-addressing mode of the network. The dual addressing mode substitutes reduced-length addresses (referred to as short addresses) for standard addresses (referred to as long addresses) for traffic whose source or destination is internal to a given virtual network topology. The required length of short addresses used for a given virtual topology is dependent on the number of devices reachable within the topology.

Dynamic load balancing for WDM-based packet networks

Abstract: We develop load balancing algorithms for WDM-based packet networks in which the average traffic between nodes is dynamically changing. In WDM-based packet networks, routers are connected to each other using wavelengths (lightpaths) to form a logical network topology. This logical topology may be reconfigured by rearranging the lightpaths connecting the routers. The goal of our load balancing algorithms is to minimize network delay by reconfiguring the logical topology. Since delay becomes unbounded as the load approaches the link capacity, delay is usually dominated by the most heavily loaded link. Therefore, our algorithms attempt to minimize the maximum link load. Even when traffic is static, deriving the optimal logical topology for a given traffic pattern is known to be NP-complete. Previous work on reconfiguration proposed heuristic algorithms to determine the "best" logical topology for the given traffic pattern and migrated to that topology using a series of reconfiguration steps. However, when traffic patterns are changing rapidly, reconfiguring the full network with every change in the traffic may be extremely disruptive. In this paper, we develop iterative reconfiguration algorithms for load balancing that track rapid changes in the traffic pattern. At each reconfiguration step, our algorithms make only a small change to the network topology, hence, minimizing the disruption to the network. We study the performance of our algorithms under several dynamic traffic scenarios and show that our algorithms perform near optimally.

Q-enhancing technique for rf CMOS active inductor

Abstract: A design technique for realising a very-high Q CMOS active inductor operating in the RF-band is described in this paper. The proposed active inductor is based on double-feedback transconductor topology in which negative feedback is used to realise inductive input impedance while positive feedback is employed to produce a negative resistance for canceling the inductor loss, hence an enhancing of the Q factor. In order to verify the effectiveness of the proposed technique, a very-high Q (Q>1,000) second-order bandpass filter has been implemented. Simulation results show that the filter exhibits stable Q factor of 12,000, the resonant frequency can be tuned from 1.007 GHz to 1.023 GHz and the input-referred third-order intercept point (IIP3) of -25 dBm (at 1.023 GHz centre frequency and 12,000 Q factor) under a 3.3 V supply voltage.

Modeling average current mode control [of power convertors]

Abstract: An averaged small signal model is presented which predicts some of the previously reported phenomena and offers new insights with analytical expressions useful for design. Detailed analysis is given for the buck converter topology with the boost and buck-boost results also provided. The modulator gain, for a first order approximation, is shown to be constant as in voltage mode control. Guidelines are presented to optimize the design of the current loop and control-to-output transfer functions are given which are necessary to compensate the voltage loop. Experimental data is provided, in the case of the buck converter, to develop and verify the model.

Topology preserving compression of 2D vector fields

Abstract: We present an algorithm for compressing 2D vector fields that preserves topology. Our approach is to simplify the given data set using constrained clustering. We employ different types of global and local error metrics including the earth mover's distance metric to measure the degradation in topology as well as weighted magnitude and angular errors. As a result, we obtain precise error bounds in the compressed vector fields. Experiments with both analytic and simulated data sets are presented. Results indicate that one can obtain significant compression with low errors without losing topology information.