Showing papers on "Topology (electrical circuits) published in 2002"

Mapping the Gnutella network

Abstract: We studied the topology and protocols of the public Gnutella network. Its substantial user base and open architecture make it a good large-scale, if uncontrolled, testbed. We captured the network's topology, generated traffic, and dynamic behavior to determine its connectivity structure and how well (if at all) Gnutella's overlay network topology maps to the physical Internet infrastructure. Our analysis of the network allowed us to evaluate costs and benefits of the peer-to-peer (P2P) approach and to investigate possible improvements that would allow better scaling and increased reliability in Gnutella and similar networks. A mismatch between Gnutella's overlay network topology and the Internet infrastructure has critical performance implications.

Modeling the Internet's large-scale topology

Abstract: Network generators that capture the Internet's large-scale topology are crucial for the development of efficient routing protocols and modeling Internet traffic. Our ability to design realistic generators is limited by the incomplete understanding of the fundamental driving forces that affect the Internet's evolution. By combining several independent databases capturing the time evolution, topology, and physical layout of the Internet, we identify the universal mechanisms that shape the Internet's router and autonomous system level topology. We find that the physical layout of nodes form a fractal set, determined by population density patterns around the globe. The placement of links is driven by competition between preferential attachment and linear distance dependence, a marked departure from the currently used exponential laws. The universal parameters that we extract significantly restrict the class of potentially correct Internet models and indicate that the networks created by all available topology generators are fundamentally different from the current Internet.

A comparison of high-power converter topologies for the implementation of FACTS controllers

Abstract: This paper compares four power converter topologies for the implementation of flexible AC transmission system (FACTS) controllers: three multilevel topologies (multipoint clamped (MPC), chain, and nested cell) and the well-established multipulse topology. In keeping with the need to implement very-high-power inverters, switching frequency is restricted to line frequency. The study addresses device count, DC filter ratings, restrictions on voltage control, active power transfer through the DC link, and balancing of DC-link voltages. Emphasis is placed on capacitor sizing because of its impact on the cost and size of the FACTS controller. A method for the dimensioning the DC capacitor filter is presented. It is found that the chain converter is attractive for the implementation of a static compensator or a static synchronous series compensator. The MPC converter is attractive for the implementation of a unified power flow controller or an interline power flow controller, but a special arrangement is required to overcome the limitations on voltage control.

Adaptive synthesis and design of resonator filters with source/load-multiresonator coupling

Abstract: The paper presents a universal and comprehensive synthesis technique of coupled resonator filters with source/load-multiresonator coupling. The approach is based on repeated analyses of a circuit with the desired topology; no similarity transformation is needed. Restrictions imposed by the implementation on the coupling coefficients such as signs and orders of magnitudes are straightforwardly handled within this technique. The technique is then used to synthesize and design filters with full or almost full coupling matrices by selecting, among the infinite number of solutions, the matrix that corresponds to the actual implementation. In such cases, analytical techniques and those based on similarity transformations cannot be used since they provide no mechanism to constrain individual coupling coefficients in order to discriminate between two full coupling matrices, which are both solutions to the synthesis problem. Using the technique described in this paper, a filter designer can extract the coupling matrix of a filter of arbitrary order and topology while enforcing relevant constraints. There is no need to master all the different existing similarity-transformation-based techniques and the topologies to which they are applicable. For the first time, detailed investigations of parasitic coupling effects, for either compensation or utilization, are made possible. The method is applied to the synthesis of a variety of filters, some of which are then designed and built and their response measured.

Analysis and design considerations of a load and line independent zero voltage switching full bridge DC/DC converter topology

Abstract: The analysis and design of a zero voltage switching (ZVS) full bridge DC/DC power converter topology is presented in this paper. The converter topology presented here employs an asymmetrical auxiliary circuit consisting of a few passive components. With this auxiliary circuit, the full bridge converter can achieve ZVS independent of line and load conditions. The operating principle of the circuit is demonstrated, and the steady state analysis is performed. Based on the analysis, a criterion for optimal design is given. Experiment and simulation on a 350-400 V to 55 V, 500 W prototype converter operated at 100 kHz verify the design and show an overall efficiency of greater than 97% at full load.

Coupled-inductor design optimization for fast-response low-voltage DC-DC converters

Abstract: Multiphase voltage regulator modules (VRMs) for microprocessor power delivery with coupled output inductors are discussed. Strong coupling is shown to be feasible and effective at reducing ripple if the correct magnetic topology is used. For more than two phases, this can be a "ladder" core with windings around each rung. Typical ripple reduction is better than a factor of six with no effect on response time. One can also chose to improve response time while still significantly reducing ripple. A simultaneous numerical optimization of the magnetics and the circuit is used to minimize loss in a fast-response 100 A design.

Topology for hybrid multilevel inverter

Abstract: A new topology for a hybrid multilevel inverter is presented, which significantly increases the level number of the output waveform and thereby dramatically reduces the low-order harmonics and total harmonic distortion. To the best of the authors' knowledge, the presented topology has the greatest level number for a given number of stages. Moreover, the stage with higher DC link voltage has lower switching frequency; and thereby reduces the switching losses. Comparison of the results of various multilevel inverters is investigated to reflect the merits of the presented topology. The details of the PWM control using the harmonic elimination technique for the hybrid inverter are presented and confirmed by both simulation and experimental results.

A new matrix converter motor (MCM) for industry applications

Abstract: The trend in electrical drives is to integrate the frequency converter, the electrical motor, and even the gear or the pump into a single unit, in order to reduce the costs, to increase the overall efficiency and the equipment reliability. This paper presents the first integrated regenerative frequency converter motor for industry applications, based on a matrix converter topology. The low volume, the sinusoidal input current, the bidirectional power flow, and the lack of the bulky and limited-lifetime electrolytic capacitors recommend this topology for this application. This paper shows how the matrix converter disadvantages-the lack of bidirectional power devices, the lower voltage transfer ratio, and the overvoltages caused by the input filter during power-up-that have delayed the industrial implementation have been overcome. In order to demonstrate the validity of the solution, a 4-kW matrix converter motor prototype is built using a standard frequency converter motor enclosure for testing the requirements for an industrial drive. The tests demonstrate the good performance of the drive.

A magnetic-less DC-DC converter for dual voltage automotive systems

Abstract: The automotive industry is moving toward 42 volt to meet the more electric needs. Several dual voltage (42 and 14 volt) architectures have been proposed for the transition and accommodation of 14-volt loads. A DC-DC converter that connects the 42 and 14 volt architectures is one key device in any dual voltage architecture. This paper presents a compact, efficient, magnetic-less bi-directional DC-DC converter for dual voltage (42/14 Volt) automotive systems. The DC-DC converter is based on the generalized multilevel converter topology having the ability to balance battery voltages, emit zero or low electromagnetic interference (EMI), and have low cost by using low-voltage metal oxide field effect transistors (MOSFETs). The main circuit of the DC-DC converter is analyzed and its control scheme is presented in the paper. A self-powered gate drive circuit is developed for the DC-DC converter to reduce costs, signal connections, and circuit complexity. A prototype has been built and experimental results are presented.

Systems and methods for constructing multi-layer topological models of computer networks

Abstract: A network management system includes a fault diagnosis engine, a topology mapper, an impact analyzer and a help desk system. The topology mapper includes a discovery module, a memory, and a presentation module. The discovery module is constructed and arranged to discover network elements in a communications network. The memory constructed and arranged to store topology data received from the discovery module. The presentation module constructed and arranged to present data related to topology of the communication network.

Matrix converter topologies with reduced number of switches

Abstract: A direct AC-to-AC converter commonly termed a matrix converter has a simple structure and many attractive features. However, the complexity of its conventional PWM strategy is prone to commutation failure, which is a factor that keeps it from being utilized in industry. This paper focuses on several alternative dual-bridge matrix topologies which do not possess this problem. First, these converters have the same characteristics as a conventional matrix converter, such as four-quadrant operation, unity input power factor, no DC-link capacitor, and high quality voltage/current waveforms. Second, the number of switches can be reduced thus reducing the cost. Third, the switches on the line side can turn on and off at zero current, they do not have any difficult commutation problems. Lastly, the complexity of the clamp circuit in these topologies can be greatly simplified thereby further reducing the cost. This paper introduces several topologies with a reduced number of switches and analyzes the characteristics of this converter family. Simulation and experimental results of a 9-switch topology are provided to verify its feasibility.

A new hybrid active power filter (APF) topology

Abstract: In this paper, a new hybrid active power filter topology is presented. A higher-voltage, low-switching frequency insulated gate bipolar transistor (IGBT) inverter and a lower-voltage high-switching frequency metal oxide semiconductor field effect transistor (MOSFET) inverter are used in combination to achieve harmonic current compensation. The function of the IGBT inverter is to support utility fundamental voltage and to compensate for the fundamental reactive power. The MOSFET inverter fulfills the function of harmonic current compensation. To further reduce cost and to simplify control, the IGBT and MOSFET inverters share the same DC-link via a split capacitor bank. With this approach harmonics can be cancelled over a wide frequency range. Compared to the conventional APF topology, the proposed approach employs lower dc-link voltage and generates less noise. Simulation and experimental results show that the proposed active power filter topology is capable of compensating for the load harmonics.

System and method dynamic cluster membership in a distributed data system

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

On optimal traffic grooming in WDM rings

Abstract: We consider the problem of designing a virtual topology to minimize electronic routing, that is, grooming traffic, in wavelength routed optical rings. The full virtual topology design problem is NP-hard even in the restricted case where the physical topology is a ring, and various heuristics have been proposed in the literature for obtaining good solutions, usually for different classes of problem instances. We present a new framework which can be used to evaluate the performance of heuristics and which requires significantly less computation than evaluating the optimal solution. This framework is based on a general formulation of the virtual topology problem, and it consists of a sequence of bounds, both upper and lower, in which each successive bound is at least as strong as the previous one. The successive bounds take larger amounts of computation to evaluate, and the number of bounds to be evaluated for a given problem instance is only limited by the computational power available. The bounds are based on decomposing the ring into sets of nodes arranged in a path and adopting the locally optimal topology within each set. While we only consider the objective of minimizing electronic routing in this paper, our approach to obtaining the sequence of bounds can be applied to many virtual topology problems on rings. The upper bounds we obtain also provide a useful series of heuristic solutions.

HyperCuP: hypercubes, ontologies, and efficient search on peer-to-peer networks

Abstract: Peer-to-peer networks are envisioned to be deployed for a wide range of applications However, P2P networks evolving in an unorganized manner suffer from serious scalability problems, limiting the number of nodes in the network, creating network overload and pushing search times to unacceptable limits We address these problems by imposing a deterministic shape on P2P networks: We propose a graph topology which allows for very efficient broadcast and search, and we describe a broadcast algorithm that exploits the topology to reach all nodes in the network with the minimum number of messages possible We provide an efficient topology construction and maintenance algorithm which, crucial to symmetric peer-to-peer networks, does neither require a central server nor super nodes in the network Nodes can join and leave the self-organizing network at any time, and the network is resilient against failure Moreover, we show how our scheme can be made even more efficient by using a global ontology to determine the organization of peers in the graph topology, allowing for efficient concept-based search

Distributed topology control algorithm for multihop wireless networks

Abstract: We present a network initialization algorithm for wireless networks with distributed intelligence. Each node (agent) has only local, incomplete knowledge and it must make local decisions to meet a predefined global objective. Our objective is to use power control to establish a topology based on the relative neighborhood graph which has good overall performance in terms of power usage, low interference, and reliability.

System and method for topology manager employing finite state automata for dynamic cluster formation

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Single phase three-level power factor correction circuit with passive lossless snubber

Abstract: Multilevel conversion techniques, power factor correction (PFC) techniques and soft switching techniques are the three research hot points of power electronics. The paper proposes a single phase three-level PFC circuit with passive lossless snubbers which embodies these trends. Firstly, the three-level buck and boost topologies are derived from one bridge leg of the traditional diode clamped three-level inverters. Then, a single phase three-level PFC circuit is presented based on the three-level boost topology, and the principle and implementation approaches of the three-level PFC circuit are described. To realize the soft switching of the main switches and freewheeling diodes, two passive lossless snubber cells are added to the circuit. The operating principle and design considerations of the new circuit are discussed in detail. Finally, a 2 kW prototype of the single phase three-level PFC with the passive lossless snubber is built and tested. The simulated and experimental results indicate that the proposed circuit can realize the function of three-level PFC, increase system efficiency and have no over-voltage stresses on main power switches. Moreover, the power factor of the proposed circuit with the passive lossless snubber is higher than that of the circuit without the snubber.

Fluctuation-driven dynamics of the internet topology.

Abstract: We study the dynamics of the Internet topology based on empirical data on the level of the autonomous systems. It is found that the fluctuations occurring in the stochastic process of connecting and disconnecting edges are important features of the Internet dynamics. The network's overall growth can be described approximately by a single characteristic degree growth rate g(eff) approximately 0.016 and the fluctuation strength sigma(eff) approximately 0.14, together with the vertex growth rate alpha approximately 0.029. A stochastic model which incorporates these values and an adaptation rule newly introduced reproduces several features of the real Internet topology such as the correlations between the degrees of different vertices.

A general three-phase PFC controller for rectifiers with a parallel-connected dual boost topology

Abstract: A general constant-frequency power-factor-correction (PFC) controller is proposed for three-phase rectifiers with parallel-connected dual-boost topologies. This paper shows that unity power factor and low current distortion in all three phases can be realized by one-cycle control using one integrator with reset along with a few near and logic components. This new extension of one-cycle control provides the core PFC function to the dual-boost topologies. It does not require multipliers, as used in most other control approaches to scale the current reference according to the output power level. In each 60/spl deg/ of AC line cycle, only two switches are switched at high frequency; therefore the switching losses are significantly reduced. All switches are switched at low current, which results in reduced current ratings. This control method is simple and general. It is applicable to three-phase rectifiers that can be decoupled into parallel-connected dual-boost topologies by slight modification of the logic circuit. This control method is verified by experimental results. The proposed controller is suitable to be integrated into a three-phase PFC control chip.

A novel topology design scheme for the multi-physics problems of electro-thermally actuated compliant micromechanisms

Abstract: In addition to the advantages of embedded actuation, large forces and displacements, and ease of microfabrication, one more attractive feature of electro-thermally actuated compliant mechanisms is their suitability for systematic synthesis directly from behavioral specifications. We and other groups have presented topology optimization methods for similar problems. In this paper, we describe a new design parameterization scheme for the topology optimization problem involving three energy domains (electrical, thermal, and elastostatic) and multiple materials. We also show how topology-dependent modeling such as convection through side surfaces can be dealt with in a design technique wherein the topology is varied.

Design considerations for a 48 V fuel cell to split single phase inverter system with ultracapacitor energy storage

Abstract: Fuel cells are a versatile, renewable energy source that can be used in a wide range of applications. In this paper, topologies for a 10 kW inverter system with a low voltage fuel cell input are evaluated based on simplicity, performance, and cost. This particular fuel cell system is intended for household stand-alone power generation. The inverter proposed has a nominal fuel cell input of 48 VDC and is capable of two single phase 120 VAC outputs and one 240 Vac output. Different topology options are explored for the DC-DC converter and the inverter stages, and one combination is evaluated in detail. There is a clear topological choice for the DC-DC converter, but there are a couple of options that work well for the inverter stage. Different choices for energy storage also exist and a good alternative to batteries is presented. The chosen topology contains two modular units, which are supplemented with a set of ultracapacitors at the input for transient conditions. Each module consists of a full-bridge phase-shifted front-end and a half-bridge inverter. Experimental results are displayed for several load conditions.

System and method for dynamic cluster adjustment to node failures in a distributed data system

Abstract: A distributed system provides for separate management of dynamic cluster membership and distributed data. Nodes of the distributed system may include a state manager and a topology manager. A state manager handles data access from the cluster. A topology manager handles changes to the dynamic cluster topology. The topology manager enables operation of the state manager by handling topology changes, such as new nodes to join the cluster and node members to exit the cluster. A topology manager may follow a static topology description when handling cluster topology changes. Data replication and recovery functions may be implemented, for example to provide high availability.

Nonlinear magnetic circuit analysis for a novel stator-doubly-fed doubly-salient machine

Abstract: Summary form only given. The doubly-salient permanent-magnet (DSPM) machine takes the advantages of high power density and high efficiency, but still suffers from limited constant-power speed range and high PM material cost. We propose a novel topology, namely the stator-doubly-fed doubly-salient (SDFDS) machine, which not only solves the problems of the DSPM machine, but also offers the flexibility to on-line optimize the efficiency. In order to effectively analyze and efficiently optimize the proposed machine, a new nonlinear magnetic circuit (NMC) analysis approach is also proposed.

A Flexible DSTATCOM Operating in Voltage or Current Control Mode

Abstract: The topology and control are discussed of a distribution static compensator (DSTATCOM) that can be operated flexibly in the voltage or current control mode. In the voltage control mode, the DSTATCOM can force the voltage of a distribution bus to be balanced sinusoids. In the current control mode, it can cancel distortion caused by the load, such that current drawn by the compensated load is pure balanced sinusoid. Both these objectives are achieved, irrespective of unbalance and harmonic distortions in load currents or source voltages. The chosen DSTATCOM topology includes three single-phase voltage source inverters connected in parallel to a filter-capacitor, which allows the high-frequency component of the current to pass. A switching control scheme is proposed, and its suitability is proved for this problem. The proposed scheme is verified using computer simulation studies.

Help desk systems and methods for use with communications networks

Abstract: A network management system includes a fault diagnosis system, a topology mapper, an impact analyzer and a help desk system. The a help desk system includes a user interaction module, and a fault diagnosis interaction module. The user interaction module is constructed and arranged to automatically communicate with a user. The fault diagnosis interaction module is constructed and arranged to communicate with a fault diagnosis system.

Implementing the MPI Process Topology Mechanism

Abstract: The topology functionality of the Message Passing Interface (MPI) provides a portable, architecture-independent means for adapting application programs to the communication architecture of the target hardware. However, current MPI implementations rarely go beyond the most trivial implementation, and simply performs no process remapping. We discuss the potential of the topology mechanism for systems with a hierarchical communication architecture like clusters of SMP nodes. The MPI topology functionality is a weak mechanism, and we argue about some of its shortcomings. We formulate the topology optimization problem as a graph embedding problem , and show that for hierarchical systems it can be solved by graph partitioning . We state the properties of a new heuristic for solving both the embedding problem and the "easier" graph partitioning problem. The graph partitioning based framework has been fully implemented in MPI/SX for the NEC SX-series of parallel vector computers. MPI/SX is thus one of very few MPI implementations with a non-trivial topology functionality. On a 4 node NEC SX-6 significant communication performance improvements are achieved with synthetic MPI benchmarks.

A hysteresis current control for single-phase multilevel voltage source inverters: PLD implementation

Abstract: In most high-performance applications of voltage source pulse-width modulation inverters, current control is an essential part of the overall control system. In this paper, a hysteresis current control technique for a single-phase five-level inverter with flying-capacitor topology is proposed. Logic controls and a programmable logic device are suitable for handling a large number of switches and implementation of state transitions. This method also considers how to improve unbalanced voltages of capacitors using voltage vectors in order to minimize switching losses. The simulation and experimental results describe and verify the current control technique for the inverter.

A three-leg voltage source inverter for two-phase AC motor drive systems

Abstract: This paper investigates the use of a three-leg voltage source inverter topology for supplying two-phase induction motors. The paper also presents two pulse width modulation techniques for voltage control and a quasi time-invariant model to describe an unbalanced two-phase machine. The correctness of the proposed drive system was demonstrated through experimental results obtained with a laboratory prototype.

A three-level MOSFET inverter for low power drives

Abstract: This paper proposes operating a three-level neutral-point-clamped (NPC) inverter using a two-level pulsewidth-modulation method. This allows for the clamping diodes to be rated at a fraction of the main switches due to their low average current requirement. The use of a bootstrap charge pump as a low-cost method to obtain the isolated gate drive power supplies is extended for use with the NPC topology. Using this control method and circuits, an inverter based on high-volume, low-cost, low-voltage power MOSFETs is experimentally demonstrated as a possible economic alternative to an insulated-gate-bipolar-transistor-based drive for 120-Vrms-supplied systems.