Showing papers on "Topology (electrical circuits) published in 2003"

An innovative modular multilevel converter topology suitable for a wide power range

Abstract: This paper presents a new multilevel converter topology suitable for very high voltage applications, especially network interties in power generation and transmission. The fundamental concept and the applied control scheme is introduced. Simulation results of a 36 MW-network intertie illustrate the efficient operating characteristics. A suitable structure of the converter-control is proposed.

Design and analysis of an MST-based topology control algorithm

Abstract: In this paper, we present a minimum spanning tree (MST) based topology control algorithm, called local minimum spanning tree (LMST), for wireless multi-hop networks. In this algorithm, each node builds its local minimum spanning tree independently and only keeps on-tree nodes that are one-hop away as its neighbors in the final topology. We analytically prove several important properties of LMST: (1) the topology derived under LMST preserves the network connectivity; (2) the node degree of any node in the resulting topology is bounded by 6; and (3) the topology can be transformed into one with bidirectional links (without impairing the network connectivity) after removal of all uni-directional links. These results are corroborated in the simulation study.

A multiple-input DC-DC converter topology

Abstract: A new topology for multiple energy source conversion is presented. The topology is capable of interfacing sources of different voltage-current characteristics to a common load, while achieving a low part count. A fixed frequency switching strategy is investigated and the resulting operating modes are analyzed. The analysis is verified by experimentation. The results show that the converter is an enabling technology for power diversification and optimization.

Power laws and the AS-level Internet topology

Abstract: In this paper, we study and characterize the topology of the Internet at the autonomous system (AS) level. First, we show that the topology can be described efficiently with power laws. The elegance and simplicity of the power laws provide a novel perspective into the seemingly uncontrolled Internet structure. Second, we show that power laws have appeared consistently over the last five years. We also observe that the power laws hold even in the most recent and more complete topology with correlation coefficient above 99% for the degree-based power law. In addition, we study the evolution of the power-law exponents over the five-year interval and observe a variation for the degree-based power law of less than 10%. Third, we provide relationships between the exponents and other topological metrics.

Single-inductor multiple-output switching converters with time-multiplexing control in discontinuous conduction mode

Abstract: An integrated single-inductor dual-output boost converter is presented. This converter adopts time-multiplexing control in providing two independent supply voltages (3.0 and 3.6 V) using only one 1-/spl mu/H off-chip inductor and a single control loop. This converter is analyzed and compared with existing counterparts in the aspects of integration, architecture, control scheme, and system stability. Implementation of the power stage, the controller, and the peripheral functional blocks is discussed. The design was fabricated with a standard 0.5-/spl mu/m CMOS n-well process. At an oscillator frequency of 1 MHz, the power conversion efficiency reaches 88.4% at a total output power of 350 mW. This topology can be extended to have multiple outputs and can be applied to buck, flyback, and other kinds of converters.

Topology management in ad hoc networks

Abstract: The efficiency of a communication network depends not only on its control protocols, but also on its topology. We propose a distributed topology management algorithm that constructs and maintains a backbone topology based on a minimal dominating set (MDS) of the network. According to this algorithm, each node determines the membership in the MDS for itself and its one-hop neighbors based on two-hop neighbor information that is disseminated among neighboring nodes. The algorithm then ensures that the members of the MDS are connected into a connected dominating set (CDS), which can be used to form the backbone infrastructure of the communication network for such purposes as routing. The correctness of the algorithm is proven, and the efficiency is compared with other topology management heuristics using simulations. Our algorithm shows better behavior and higher stability in ad hoc networks than prior algorithms.

Strong minimum energy topology in wireless sensor networks: NP-completeness and heuristics

Abstract: Wireless sensor networks have recently attracted lots of research effort due to the wide range of applications. These networks must operate for months or years. However, the sensors are powered by battery, which may not be able to be recharged after they are deployed. Thus, energy-aware network management is extremely important. In this paper, we study the following problem: Given a set of sensors in the plane, assign transmit power to each sensor such that the induced topology containing only bidirectional links is strongly connected. This problem is significant in both theory and application. We prove its NP-completeness and propose two heuristics: power assignment based on minimum spanning tree (denoted by MST) and incremental power. We also show that the MST heuristic has a performance ratio of 2. Simulation study indicates that the performance of these two heuristics does not differ very much, but; on average, the incremental power heuristic is always better than MST.

Varactor-loaded transmission-line phase shifter at C-band using lumped elements

Abstract: The design of varactor-loaded transmission-line phase shifters using lumped elements is discussed in this paper. A monolithic-microwave integrated-circuit (MMIC) phase shifter is fabricated to verify the proposed topology. Only one control voltage is required for phase control. Within a continuously adjustable phase-control range of 360/spl deg/ and a frequency range from 5 to 6 GHz, a low transmission loss of 4 dB/spl plusmn/1.7 dB is measured. The phase shifter is realized with a commercial 0.6-/spl mu/m GaAs MESFET process and requires a chip area of only 0.8 mm/sup 2/. To the knowledge of the authors, the best results reported to date are reached for a continuously adjustable passive phase shifter with comparable circuit size. The presented circuit is well suited to wireless adaptive antenna transceivers, operating in accordance with the 802.11a, high-performance radio local-area-network and high-speed wireless-access-network type-a standard.

An original topology of dual-band filter with transmission zeros

Abstract: This paper reports on a new topology of high-performance dual-band filters. This topology is derived from the Dual Behavior Resonator (DBR) filter. The resulting resonator is directly dual-band. It allows the control of two bandpasses separated by a transmission zero to ensure a high rejection level between them. Moreover, two other transmission zeros are located on either side of the two bandpasses. The possibilities offered by this structure are discussed and measurements are presented to validate the method.

Isolated DC-DC converters with high-output voltage for TWTA telecommunication satellite applications

Abstract: Two alternatives for the implementation of an isolated DC-DC converter operating with a high output voltage and supplied by an unregulated low input voltage are presented in this paper. The proposed topologies are especially qualified for the implementation of travelling wave tube amplifiers (TWTA) utilized in telecommunication satellite applications due to their low mass and volume and their high-efficiency. The converters studied follow different principles and the main operational aspects of each topology are analyzed. A two-stage structure composed by a regulator connected in series with a ZVS/ZCS isolated DC-DC converter is the first topology proposed. The second topology studied is an isolated single-stage converter that continues being highly efficient even with a large input voltage variation. The experimental results obtained from two prototypes, implemented following the design procedures developed, are presented, verifying experimentally the characteristics and the analysis of the proposed structures. The prototypes are developed for an application requiring an output power of 150 W, a total output voltage of 3.2 kV and an input voltage varying from 26 V to 44 V. The minimum efficiency obtained for both converters operating at the nominal output power, is equal to 93.4% for the two-stage structure and equal to 94.1% for the single-stage converter.

Network analysis tool

Abstract: Embodiments of the invention provide a method for determining errors and metrics in a computer network. The method includes positioning an analyzer in communication with the network, capturing a data trace of the network with the analyzer, determining a network device topology from a first processing of the data trace, building user layer protocols using a second processing of the data trace and the determined device topology, determining errors in the network device topology using protocol experts applied to the user layer protocols in conjunction with the determined device topology, and displaying at least one of the device topology and the determined errors to a user.

Network analysis omniscent loop state machine

Abstract: Embodiments of the invention provide a method for analyzing a data trace representative of an FC network. The method includes determining a topology of the network, filtering the data trace for open commands that are not perceived by at least one analyzer positioned in communication with the network and eliminating devices associated with these open commands not received by an analyzer from further analysis, filtering the data trace for failed open commands and eliminating devices associated with the failed open commands from further analysis, and filtering the trace data for frames to destinations that are not received by the analyzer and eliminating devices associated with these frame from further analysis. The method further includes filtering frames transmitted when a loop is in closed state and eliminating devices associated with transmitting frames when a loop is closed from further analysis, and conducting error analysis of the network topology not eliminated by a filtering step.

A simple dc-dc converter for the power supply of a cochlear implant

Abstract: A resonant topology based on class-E is presented as the power supply of a cochlear implant. This topology has the important advantage of a small number of components and a grounded single switch. Zero voltage switching can be achieved, which significantly reduces switching losses and improves efficiency. A circuit has been designed, built and tested in order to check the feasibility of the topology for the mentioned contactless application. The results are very good, the efficiency has been clearly improved compared to the former system and the autonomy has increased.

Circuit protection system

Abstract: A circuit protection system including a CCPU (28) is provided that provides dynamic zones of protection (895, 896) for the circuit. The zones of protection (895, 896) can be based in part upon the topology of the circuit. The protection system can perform various dynamic zone protective functions for the zones of protection (895, 896).

Method and system for power line network fault detection and quality monitoring

Abstract: Fault detection and power network quality monitoring are performed for a power line network using power line communications (“PLC”) signal transceiving and data processing capabilities. Power line signals are continuously received and processed to obtain signal data representative of power line network operating conditions that are expressed in the received power line signals. The harmonic content and noise signature of the signal data are evaluated with reference to known fault signature data and power line network topology properties for detecting and identifying the location of an existing or anticipated fault in the power line network and assessing power transmission quality of the network.

Generalization of active filters for EMI reduction and harmonics compensation

Abstract: This paper analyses general active filters that can be applicable to EMI filter, active power filter, etc. It gives generalized equations presenting insertion losses and input impedances of various kinds of active filters, from which the requirements and limitations of active filters can be identified. Based on this analysis, the effectiveness of the active filters presented in several literatures is investigated. With the results of this study, an appropriate topology of an active filter for a specific application can be selected with a good rationale.

Physical topology discovery for large multisubnet networks

Abstract: Knowledge of the up-to-date physical (i.e., layer-2) topology of an Ethernet network is crucial to a number of critical network management tasks, including reactive and proactive resource management, event correlation, and root-cause analysis. Given the dynamic nature of today's IP networks, keeping track of topology information manually is a daunting (if not impossible) task. Thus, effective algorithms for automatically discovering physical network topology are necessary. In this paper, we propose the first complete algorithmic solution for discovering the physical topology of a large, heterogeneous Ethernet network comprising multiple subnets as well as (possibly) dumb or uncooperative network elements. Our algorithms rely on standard SNMP MIB information that is widely supported in modern IP networks and require no modifications to the operating system software running on elements or hosts. Furthermore, we formally demonstrate that our solution is complete for the given MIB data; that is, if the MIB information is sufficient to uniquely identify the network topology then our algorithm is guaranteed to recover it. To the best of our knowledge, ours is the first solution to provide such a strong completeness guarantee.

A new topology for unipolar brushless DC motor drive with high power factor

Abstract: A new converter topology is proposed for driving a permanent magnet brushless DC (BLDC) motor with unipolar currents. It is based on a front-end single-ended primary inductance converter (SEPIC) and a switch in series with each phase. All the switches are ground-referenced, which simplifies their gate drives. The available input voltage can be boosted for better current regulation, which is an advantage for low voltage applications. For operation with an AC supply, the SEPIC converter is designed to operate in the discontinuous conduction mode. In this operation mode, it approximates a voltage follower and the line current follows the line voltage waveform to a certain extent. The reduction in low-order harmonics and improved power factor is achieved without the use of any voltage or current sensors. The simplicity and reduced parts count of the proposed topology make it an attractive low-cost choice for many variable speed drive applications.

High-power galvanically isolated DC/DC converter topology for future automobiles

Abstract: This paper presents a 2 kW three-phase dual active bridge converter (DAB3) which converts power between 42 V and 300 V and is easily scalable up to 20 kW. The DAB3 has been selected for this application based on detailed simulations comparing different suitable topologies. The circuits investigated in this paper can operate in a soft-switching manner enabling a reduction in device switching losses and therewith an increase in switching frequency. Candidate topologies under investigation are the serial resonant converter (SR), the single-phase dual active bridge (DAB1) and the three phase dual active bridge (DAB3). Key-features are the galvanic isolation, reduced cooling costs, and the capability of transferring energy over a wide voltage range.

Analysis of energy-efficient, fair routing in wireless sensor networks through non-linear optimization

Abstract: In the area of wireless sensor networks (WSN) there is still a significant gap between theory and practice: system designs and protocols are rapidly out-pacing analysis. We develop formal computational models of a WSN based on non-linear optimization and use them to analyze the impact of fairness constraints on network performance. The optimization framework presented is very general and can also be used to analyze the optimal performance of WSN subject to other design parameters such as the topology, number of nodes, energy levels, source rates, reception power, etc. Our results show that the maximum information that can be extracted for a fixed amount of energy increases and that the minimum energy required outputting a fixed amount of information decreases as we reduce the fairness requirement in the network. We present these functions for a fixed network topology and observe that they exhibit sharp changes in gradient due to qualitative changes in optimal routes.

Resolving a distributed topology to stream data

Abstract: A distributed media session is described, which when executed, resolves a distributed topology from a request to stream data from a source device to a client device over a network. The distributed topology references a plurality of software components that, when executed, fulfill the request. At least one of the plurality of software components is executable on each of the source device and the client device.

Analysis of the buck converter for scaling the supply voltage of digital circuits

Abstract: The energy consumption in mobile systems has become a big challenge that limits high performance and autonomy in mobile systems. The dynamic voltage scaling (DVS) is a recent technique that reduces energy consumption varying dynamically the supply voltage of the system accordingly to the clock frequency. The buck topology is a good candidate to supply step variations of the output voltage meeting the DVS requirements. In this paper, it is analyzed which is the fastest output voltage evolution that can provide the Buck topology. The minimum time state transition in the buck converter and its corresponding control law are obtained applying the maximum principle or Pontryagin's principle. Design criteria for the buck topology are derived from this result. The analysis is extended to a multiphase buck converter. The minimum time control law is validated in a prototype. The measurements are in good agreement with the theoretical results.

A low-power wide dynamic range envelope detector

Abstract: We report a 75-dB 2.8-/spl mu/W 100-Hz-10-kHz envelope detector in a 1.5-/spl mu/m 2.8-V CMOS technology. The envelope detector performs input dc insensitive voltage-to-current converting rectification followed by novel nanopower current-mode peak detection. The use of a subthreshold wide linear range transconductor allows greater than 1.7-V/sub pp/ input voltage swings. We show theoretically that the optimal performance of this circuit is technology independent for the given topology and may be improved only by spending more power due to thermal noise rectification limits. A novel circuit topology is used to perform 140-nW peak detection with controllable attack and release time constants. We demonstrate good agreement of experimentally measured results with theory. The envelope detector is useful in low-power bionic implants for the deaf, hearing aids, and speech-recognition front-ends.

The influence of topology selection on the design of EV/HEV propulsion systems

Abstract: The adoption of the 42 V Powernet standard has focused substantial research effort into the design of electric machines for hybrid vehicles. This letter investigates the potential performance benefits afforded by adopting a cascaded inverter topology on the overall system and motor performance. As a particular design example, this letter shows that a cascaded inverter driving an open winding motor can increase the high-speed power density of an induction motor by 73%. For an interior permanent magnet motor, the cascaded topology can increase low-speed torque by 9% and high-speed power by up to 300%. In all cases, the power increase is achieved without increasing the phase current over a more traditional system.

A forward converter topology with independently and precisely regulated multiple outputs

Abstract: A forward converter topology with independently and precisely regulated multiple outputs is presented in this paper. In this topology, each regulated output has its own feedback control circuit that controls the appropriate synchronous rectifiers in the pertinent output stage. All output circuits are voltage-decoupled from each other, and the cross-regulation between the outputs is eliminated. Steady state analysis as well as small signal modeling is performed to understand the topology and to provide design guidance. A prototype circuit with two outputs is built, and experimental results are presented for proof-of-concept.

Dynamic power management for power optimization of interconnection networks using on/off links

Abstract: Power consumption in interconnection networks has become an increasingly important architectural issue. The links which interconnect network node routers are a major consumer of power and devour an ever-increasing portion of total available power as network bandwidth and operating frequencies upscale. In this paper, we propose a dynamic power management policy where network links are turned off and switched back on depending on network utilization in a distributed fashion. We have devised a systematic approach based on the derivation of a connectivity graph that balances power and performance for a 2D mesh topology. This coupled with a deadlock-free, fully adaptive routing algorithm guarantees packet delivery. Our approach realizes up to 37.5% reduction in overall network link power for an 8-ary 2-mesh topology with a moderate network latency increase.

A novel single-stage high-power-factor electronic ballast with symmetrical topology

Abstract: This paper proposes a novel single-stage high-power-factor high-efficiency electronic ballast with symmetrical topology for fluorescent lamps. The circuit topology originates from the integration of two half-wave rectifiers with buck-boost power-factor-correction converters and a half-bridge series-resonant parallel-loaded inverter. A high power factor at the input line is assured by operating the buck-boost converters in discontinuous conduction mode. With symmetrical operation and carefully designed circuit parameters, zero-voltage switching on the active power switches of the inverter can be retained to achieve high circuit efficiency. The design equations are derived from the analyzed results based on fundamental approximation, and then an easy-to-use design tool is provided accordingly under considerations of filament heating and ignition. A prototype circuit designed for two T9-40W rapid-start fluorescent lamps is built and tested to verify the analytical predictions. Satisfactory performance is obtained from the experimental results.