Showing papers on "Topology (electrical circuits) published in 2004"

Achieving minimum length scale in topology optimization using nodal design variables and projection functions

Abstract: A methodology for imposing a minimum length scale on structural members in discretized topology optimization problems is described. Nodal variables are implemented as the design variables and are projected onto element space to determine the element volume fractions that traditionally define topology. The projection is made via mesh independent functions that are based upon the minimum length scale. A simple linear projection scheme and a non-linear scheme using a regularized Heaviside step function to achieve nearly 0–1 solutions are examined. The new approach is demonstrated on the minimum compliance problem and the popular SIMP method is used to penalize the stiffness of intermediate volume fraction elements. Solutions are shown to meet user-defined length scale criterion without additional constraints, penalty functions or sensitivity filters. No instances of mesh dependence or checkerboard patterns have been observed. Copyright © 2004 John Wiley & Sons, Ltd.

Cascaded DC-DC converter connection of photovoltaic modules

Abstract: New residential scale photovoltaic (PV) arrays are commonly connected to the grid by a single dc-ac inverter connected to a series string of pv panels, or many small dc-ac inverters which connect one or two panels directly to the ac grid. This paper proposes an alternative topology of nonisolated per-panel dc-dc converters connected in series to create a high voltage string connected to a simplified dc-ac inverter. This offers the advantages of a "converter-per-panel" approach without the cost or efficiency penalties of individual dc-ac grid connected inverters. Buck, boost, buck-boost, and Cu/spl acute/k converters are considered as possible dc-dc converters that can be cascaded. Matlab simulations are used to compare the efficiency of each topology as well as evaluating the benefits of increasing cost and complexity. The buck and then boost converters are shown to be the most efficient topologies for a given cost, with the buck best suited for long strings and the boost for short strings. While flexible in voltage ranges, buck-boost, and Cu/spl acute/k converters are always at an efficiency or alternatively cost disadvantage.

A new ZVS bidirectional DC-DC converter for fuel cell and battery application

Abstract: This paper presents a new zero-voltage-switching (ZVS) bidirectional dc-dc converter. Compared to the traditional full and half bridge bidirectional dc-dc converters for the similar applications, the new topology has the advantages of simple circuit topology with no total device rating (TDR) penalty, soft-switching implementation without additional devices, high efficiency and simple control. These advantages make the new converter promising for medium and high power applications especially for auxiliary power supply in fuel cell vehicles and power generation where the high power density, low cost, lightweight and high reliability power converters are required. The operating principle, theoretical analysis, and design guidelines are provided in this paper. The simulation and the experimental verifications are also presented.

The rich-club phenomenon in the Internet topology

Abstract: We show that the Internet topology at the autonomous system (AS) level has a rich-club phenomenon. The rich nodes, which are a small number of nodes with large numbers of links, are very well connected to each other. The rich-club is a core tier that we measured using the rich-club connectivity and the node-node link distribution. We obtained this core tier without any heuristic assumption between the ASs. The rich-club phenomenon is a simple qualitative way to differentiate between power law topologies and provides a criterion for new network models. To show this, we compared the measured rich-club of the AS graph with networks obtained using the Baraba/spl acute/si-Albert (BA) scale-free network model, the Fitness BA model and the Inet-3.0 model.

Does topology control reduce interference

Abstract: Topology control in ad-hoc networks tries to lower node energy consumption by reducing transmission power and by confining interference, collisions and consequently retransmissions. Commonly low interference is claimed to be a consequence to sparseness of the resulting topology. In this paper we disprove this implication. In contrast to most of the related work claiming to solve the interference issue by graph sparseness without providing clear argumentation or proofs, we provide a concise and intuitive definition of interference. Based on this definition we show that most currently proposed topology control algorithms do not effectively constrain interference. Furthermore we propose connectivity-preserving an spanner constructions that are interference-minimal.

A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider

Abstract: An injection-locked oscillator topology is presented, based on MOS switches directly coupled to the LC tank of well-known LC oscillators. The direct injection-locking scheme features wide locking ranges, a very low input capacitance, and highest frequency capability. The direct locking and the tradeoff between power consumption and tank quality factor is verified through three test circuits in 0.13-/spl mu/m standard CMOS, aiming at input frequency ranges of 50, 40, and 15 GHz. The 40- and 50-GHz dividers consume 3 mW with locking ranges of 80 MHz and 1.5 GHz. The 15-GHz divider consumes 23 mW and features a locking range of 2.8 GHz.

Fault-tolerant voltage-fed PWM inverter AC motor drive systems

Abstract: This paper shows how to integrate fault compensation strategies into two different types of configurations of induction motor drive systems. The proposed strategies provide compensation for open-circuit and short-circuit failures occurring in the converter power devices. The fault compensation is achieved by reconfiguring the power converter topology with the help of isolating and connecting devices. These devices are used to redefine the post-fault converter topology. This allows for continuous free operation of the drive after isolation of the faulty power switches in the converter. Experimental results demonstrate the validity of the proposed systems.

A 40-GHz frequency divider in 0.18-/spl mu/m CMOS technology

Abstract: An analysis of regenerative dividers predicts the required phase shift or selectivity for proper operation. A divider topology is introduced that employs resonance techniques by means of on-chip spiral inductors to tune out the device capacitances. Configured as two cascaded /spl divide/2 stages, the circuit achieves a frequency range of 2.3 GHz at 40 GHz while consuming 31 mW from a 2.5-V supply.

Dual-band step-impedance bandpass filter for multimode wireless LANs

Abstract: A step-impedance bandpass filter is presented for multimode wireless LANs. The filter has a new dual-band feature of two tunable passbands at desired frequencies and high out-of-band suppression, generated by incorporating step-impedance resonators in a comb-filter topology. It saves more than half the circuit size compared with the switch-type dual-band topology. The simulation and measurement results show the dual-band feature of two passbands at 2.45 and 5.75 GHz with 85 dB suppression at 3.5 GHz.

Topology control in heterogeneous wireless networks: problems and solutions

Abstract: Previous work on topology control usually assumes homogeneous wireless nodes with uniform transmission ranges. In this paper, we propose two localized topology control algorithms for heterogeneous wireless multihop networks with nonuniform transmission ranges: directed relative neighborhood graph (DRNG) and directed local minimum spanning tree (DLMST). In both algorithms, each node selects a set of neighbors based on the locally collected information. We prove that (1) the topologies derived under DRNG and DLMST preserve the network connectivity; (2) the out degree of any node in the resulting topology by DLMST is bounded; while the out degree of nodes in the topology by DRNG is not bounded; and (3) the topologies generated by DRNG and DLMST preserve the network bi-directionality.

Methods for true energy-performance optimization

Abstract: This paper presents methods for efficient energy-performance optimization at the circuit and micro-architectural levels. The optimal balance between energy and performance is achieved when the sensitivity of energy to a change in performance is equal for all the design variables. The sensitivity-based optimizations minimize energy subject to a delay constraint. Energy savings of about 65% can be achieved without delay penalty with equalization of sensitivities to sizing, supply, and threshold voltage in a 64-bit adder, compared to the reference design sized for minimum delay. Circuit optimization is effective only in the region of about /spl plusmn/30% around the reference delay; outside of this region the optimization becomes too costly either in terms of energy or delay. Using optimal energy-delay tradeoffs from the circuit level and introducing more degrees of freedom, the optimization is hierarchically extended to higher abstraction layers. We focus on the micro-architectural optimization and demonstrate that the scope of energy-efficient optimization can be extended by the choice of circuit topology or the level of parallelism. In a 64-bit ALU example, parallelism of five provides a three-fold performance increase, while requiring the same energy as the reference design. Parallel or time-multiplexed solutions significantly affect the area of their respective designs, so the overall design cost is minimized when optimal energy-area tradeoff is achieved.

Neighborhood-Based Topology Recognition in Sensor Networks

Abstract: We consider a crucial aspect of self-organization of a sensor network consisting of a large set of simple sensor nodes with no location hardware and only very limited communication range. After having been distributed randomly in a given two-dimensional region, the nodes are required to develop a sense for the environment, based on a limited amount of local communication. We describe algorithmic approaches for determining the structure of boundary nodes of the region, and the topology of the region. We also develop methods for determining the outside boundary, the distance to the closest boundary for each point, the Voronoi diagram of the different boundaries, and the geometric thickness of the network. Our methods rely on a number of natural assumptions that are present in densely distributed sets of nodes, and make use of a combination of stochastics, topology, and geometry. Evaluation requires only a limited number of simple local computations.

Optimal transmission frequency for ultralow-power short-range radio links

Abstract: Analysis determining the optimal transmission frequency for maximum power transfer across a short-range wireless link is introduced, including a comparison of near-field transmission with far-field transmission. A new near-field power transfer formula has been derived, which allows direct comparison with the well-known far-field Friis transmission formula. Operating charts are presented, which provide the designer with the preferred transmission frequency as a function of distance and antenna dimensions, together with surface plots which show the power transfer for this frequency. The analysis, performed for loop antennas, has been used to evaluate the oscillator transmitter as a low-power topology. It is shown that the requirement of a high-Q factor to realize a low-power oscillator need not be contradictory to achieving optimal far-field radiation characteristics. Based on this fact an approach to sizing loop antennas for low-power oscillator transmitters is suggested.

A soft error rate analysis (SERA) methodology

Abstract: We present a soft error rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis-based approach that employs a judicious mix of probability theory, circuit simulation, graph theory and fault simulation. SERA achieves five orders of magnitude speed-up over Monte Carlo based simulation approaches with less than 5% error. Dependence of soft error rate (SER) of combinational circuits on supply voltage, clock period, latching window, circuit topology, and input vector values are explicitly captured and studied for a typical 0.18 /spl mu/m CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an "SER peaking" phenomenon in multipliers is observed where the center bits have an SER that is in order of magnitude greater than that of LSBs and MSBs.

Topology Optimisation of Aircraft Wing Box Ribs

Abstract: This paper considers the application of conventional energy based topology optimization methods for design of aircraft wing box ribs. Compared to standard topology optimization work undertaken at Airbus, the topology optimization of wing box ribs posed several additional challenges, mainly due to the wing box ribs being embedded in a redundant wing box structure. Several approaches to solving this problem have been investigated and are being reported as part of this paper, including a global analysis/optimization approach and two local analysis/optimization approaches. The paper also deals with both the selection of a suitable objective/constraint function formulation for topology optimization and selection of a suitable formulation for handling multiple load cases in topology optimization, but does not deal with any detailed sizing optimization of topology optimized designs.

A Distributed TDMA Slot Assignment Algorithm for Wireless Sensor Networks

Abstract: Wireless sensor networks benefit from communication protocols that reduce power requirements by avoiding frame collision. Time Division Media Access methods schedule transmission in slots to avoid collision, however these methods often lack scalability when implemented in \emph{ad hoc} networks subject to node failures and dynamic topology. This paper reports a distributed algorithm for TDMA slot assignment that is self-stabilizing to transient faults and dynamic topology change. The expected local convergence time is O(1) for any size network satisfying a constant bound on the size of a node neighborhood.

Design considerations for CMOS low-noise amplifiers

Abstract: A low-noise amplifier is the first active stage of a CMOS RF receiver. The inductively degenerated common-source LNA (CS-LNA) topology is currently popular because it achieves high gain, low noise figure, etc. The amplifier's performance is reviewed and the optimum Q value that gives the minimum noise figure is derived. It is then compared to the conventional common-gate LNA (CG-LNA) in terms of gain, noise figure, input matching, reverse isolation and stability. Finally, a general g/sub m/-boosted design technique for common-gate RF circuits is introduced that provides lower noise figure and power consumption than the conventional CS-LNA and CG-LNA stages; it also preserves the CG-LNA insensitivity to parasitic input capacitances. In view of CMOS scaling, the CG-LNA topology is attractive for future higher frequency and/or lower power designs.

Adapting physical carrier sensing to maximize spatial reuse in 802.11 mesh networks

Abstract: Spatial reuse in a mesh network can allow multiple communications to proceed simultaneously, hence proportionally improve the overall network throughput. To maximize spatial reuse, the MAC protocol must enable simultaneous transmitters to maintain the minimal separation distance that is sufficient to avoid interference. This paper demonstrates that physical carrier sensing enhanced with a tunable sensing threshold is effective at avoiding interference in 802.11 mesh networks without requiring the use of virtual carrier sensing. We present an analytical model for deriving the optimal sensing threshold given network topology, reception power and data rate. A distributed adaptive scheme is also presented to dynamically adjust the physical carrier sensing threshold based on periodic estimation of channel conditions in the network. Simulation results are shown for large-scale 802.11b and 802.11a networks to validate both the analytical model and the adaptation scheme. It is demonstrated that the enhanced physical carrier sensing mechanism effectively improves network throughput by maximizing the potential of spatial reuse. With dynamically tuned physical carrier sensing, the end to end throughput approaches 90% of the predicted theoretical upper-bound assuming a perfect MAC protocol, for a regular chain topology of 90 nodes. Copyright © 2004 John Wiley & Sons, Ltd.

Topology discovery in heterogeneous IP networks: the NetInventory system

Abstract: Knowledge of the up-to-date physical topology of an IP network is crucial to a number of critical network management tasks, including reactive and proactive resource management, event correlation, and root-cause analysis. Given the dynamic nature of today's IP networks, keeping track of topology information manually is a daunting (if not impossible) task. Thus, effective algorithms for automatically discovering physical network topology are necessary. Earlier work has typically concentrated on either 1) discovering logical (i.e., layer-3) topology, which implies that the connectivity of all layer-2 elements (e.g., switches and bridges) is ignored, or 2) proprietary solutions targeting specific product families. In this paper, we present novel algorithms for discovering physical topology in heterogeneous (i.e., multi-vendor) IP networks. Our algorithms rely on standard SNMP MIB information that is widely supported by modern IP network elements and require no modifications to the operating system software running on elements or hosts. We have implemented the algorithms presented in this paper in the context of the NetInventory topology-discovery tool that has been tested on Lucent's own research network. The experimental results clearly validate our approach, demonstrating that our tool can consistently discover the accurate physical network topology with reasonably small running-time requirements even for fairly large network configurations.

Overview of PI-based solutions for the control of the dc-buses of a single-phase H-bridge multilevel active rectifier

Abstract: The H-bridge based multilevel active rectifier is an attractive topology that allows feeding of multiple dc loads. However the balancing of the dc buses often causes instability problems. The main control problem is to manage n+1 state variables (one current plus n dc voltages) with only n switching functions. In this paper several PI-based solutions are reviewed through simulations and experimental tests.

A very low-power quadrature VCO with back-gate coupling

Abstract: A new quadrature voltage-controlled oscillator (QVCO) topology is proposed where the back-gates of the core transistors are used as coupling terminals. The use of back-gates reduces the power dissipation and removes the additional noise contributions compare to the conventional coupling transistor based topology. The advantages of the proposed QVCO topology in comparison with prior works are exploited based on simulation. A QVCO based on the proposed topology with additional design ideas has been implemented using a 0.18-/spl mu/m triple-well technology for 1 GHz-band operation, and measurement shows the phase noise of -120 dBc/Hz at 1-MHz offset with output power of 2.5 dBm, while dissipating only 3 mA for the whole QVCO from 1.8-V supply.

Enhancements to the time synchronization standard IEEE-1588 for a system of cascaded bridges

Abstract: The IEEE-1588 standard for a high precision time synchronization now exists since 2002. For using this standard in bridged networks a so-called boundary clock is defined, where the local clock adjustment can be modeled by a corresponding control loop. At the field level of industrial automation systems, the line topology is very important. By using Ethernet at the field level, the resulting chain of bridges leads to a cascade of control loops and may lead to instabilities and deviations of the distributed clocks, which are not acceptable. For this application a bypass clock instead of the boundary clock is proposed as an enhancement of the IEEE-1588 standard. The effectiveness of this extension to be evaluated by simulation technique.

A novel single-stage full-bridge buck-boost inverter

Abstract: A novel single-stage full-bridge series-resonant buck-boost inverter (FB-SRBBI) is proposed in this paper. The proposed inverter only includes a full-bridge topology and a LC resonant tank without auxiliary switches. The output voltage of the proposed inverter can be larger or lower than the dc input voltage, depending on the instantaneous duty-cycle. This property is not found in the classical voltage source inverter, which produces an ac output instantaneous voltage always lower than the dc input voltage. The proposed inverter circuit topology provides the main switch for turn-on at ZCS by a resonant tank. The nonlinear control strategy is designed against the input dc perturbation and achieves well dynamic regulation. An average approach is employed to analyze the system. A design example of 500 W dc/ac inverter is examined to assess the inverter performance and it provides high power efficiency above 90% under the rated power.

Design, simulation and implementation of three-pole/four-pole topologies for active filters

Abstract: Three-pole/four-pole topologies of current-controlled voltage source inverters (CC-VSI) used as active filter (AF) are considered. The proposed AF system employs power balance theory, which is implemented using a TMS320C31 DSP. A four-pole topology for the AF system exhibits the facility of operating it as a three-pole device. A prototype model of the AF system has been designed and tested with a non-linear load to demonstrate its effectiveness for harmonic elimination, reactive power compensation and power-factor correction. After the control scheme was verified through extensive experimental investigations on a three-pole AF system, it was applied to demonstrate the performance of a four-pole AF system through simulation with different possibilities for the non-linear loads in field applications. Simulation and experimental results of the developed model of the AF system are given and discussed in detail.

Common mode noise modeling and analysis of dual boost PFC circuit

Abstract: To achieve high efficiency PFC front stage in switching mode power supply (SMPS), dual boost PFC (DBPFC) topology shows superior characteristics compared with traditional boost PFC, but it by nature brings higher EMI noise, especially common mode (CM) noise This paper deals with the modeling and analysis of DBPFC CM noise based on and compared with boost PFC, noise propagation equivalent circuits of both topologies are deduced, and theoretical analysis illustrates the difference Experiments are performed to validate the EMI model and analysis

Fuel cell power system and high power DC-DC converter

Abstract: This paper discusses the principle and electrical characteristics of the fuel cell, designs an innovative hybrid power system, and proposes a new DC/DC converter scheme to combine the fuel cell with the storage system. An effective converter scheme for the fuel cell is obtained by analyzing the high efficient topology as well as the phase shifted pulse-width modulation. Through comparing several different control modes of converters, a 75-kW prototype system is constructed, moreover, which steady-state operating characteristics are illustrated and discussed in detail. At last, experimental results are also shown to verify the proposed scheme.

Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers

Abstract: Several Miller compensation schemes using a current buffer in series with the compensation capacitor to modify the right-half-plane zero in fully differential two-stage CMOS operational amplifiers are analyzed. One scheme uses a current mirror as a current buffer, while the rest use a common-gate transistor as a current buffer. The gain transfer functions are derived for each topology, and approximate transfer-function coefficients are found that allow accurate estimation of the zero(s) and poles.

CLTC: a cluster-based topology control for ad hoc networks

Abstract: The topology of an ad hoc network has a significant impact on its performance in that a dense topology may induce high interference and low capacity, while a sparse topology is vulnerable to link failure and network partitioning. Topology control aims to maintain a topology that optimizes network performance while minimizing energy consumption. Existing topology control algorithms utilize either a purely centralized or a purely distributed approach. A centralized approach, although able to achieve strong connectivity (k-connectivity for k /spl ges/ 2), suffers from scalability problems. In contrast, a distributed approach, although scalable, lacks strong connectivity guarantees. We propose a hybrid topology control framework, cluster-based topology control (CLTC) that achieves both scalability and strong connectivity. By varying the algorithms utilized in each of the three phases of the framework, a variety of optimization objectives and topological properties can be achieved. In this paper, we present the CLTC framework; describe topology control algorithms based on CLTC and prove that k-connectivity is achieved using those algorithms; analyze the message complexity of an implementation of CLTC, namely, CLTC-A, and present simulation studies that evaluate the effectiveness of CLTC-A for a range of networks.

System and method for scanning a network

Abstract: Systems and methods to passively scan a network are disclosed herein. The passive scanner sniffs a plurality of packets traveling across the network. The passive scanner analyzes information from the sniffed packets to build a topology of network devices and services that are active on the network. In addition, the passive scanner analyzes the information to detect vulnerabilities in network devices and services. Finally, the passive scanner prepares a report containing the detected vulnerabilities and the topology when it observes a minimum number of sessions. Because the passive scanner operates passively, it may operate continuously without burdening the network. Similarly, it also may obtain information regarding client-side and server side vulnerabilities.

A zero voltage transition boost converter employing a soft switching auxiliary circuit with reduced conduction losses

Abstract: This paper presents a zero-voltage-transition (ZVT) boost converter using a soft switching auxiliary circuit for power factor correction (PFC) applications. The improvement over existing topologies lies in the positioning of the auxiliary circuit capacitors and the subsequent reduction in the resonant current and therefore the conduction losses as compared to other similar topologies. The proposed converter operates in two modes - Mode 1 and Mode 2. It is shown in the paper that the converter should be designed using the constraints obtained in Mode 1 to achieve low-loss switching. The converter is analyzed and characteristic curves presented which are then used in a detailed design example. Experimental results from a 250 W, 127 V input laboratory prototype switching at 100 kHz verify the design process and highlight the advantages of the proposed topology. The proposed converter is suitable for single-phase, two stage power factor correction circuits with universal input voltage range and power levels up to 3 kW.