Showing papers on "Topology (electrical circuits) published in 2006"

Family of multiport bidirectional DC¿DC converters

Abstract: Multiport DC-DC converters are of potential interest in applications such as generation systems utilising multiple sustainable energy sources. A family of multiport bidirectional DC-DC converters derived from a general topology is presented. The topology shows a combination of DC-link and magnetic coupling. This structure makes use of both methods to interconnect multiple sources without the penalty of extra conversion or additional switches. The resulting converters have the advantage of being simple in topology and have a minimum number of power devices. The proposed general topology and basic cells show several possibilities to construct a multiport converter for particular applications and provide a solution to integrate diverse sources owing to their flexibility in structure. The system features a minimal number of conversion steps, low cost and compact packaging. In addition, the control and power management of the converter by a single digital processor is possible. The centralised control eliminates complicated communication structures that would be necessary in the conventional structure based on separate conversion stages. A control strategy based on classical control theory is proposed, showing a multiple PID-loop structure. The general topology and a set of three-port embodiments are detailed.

Towards IP geolocation using delay and topology measurements

Abstract: We present Topology-based Geolocation (TBG), a novel approach to estimating the geographic location of arbitrary Internet hosts. We motivate our work by showing that 1) existing approaches, based on end-to-end delay measurements from a set of landmarks, fail to outperform much simpler techniques, and 2) the error of these approaches is strongly determined by the distance to the nearest landmark, even when triangulation is used to combine estimates from different landmarks. Our approach improves on these earlier techniques by leveraging network topology, along with measurements of network delay, to constrain host position. We convert topology and delay data into a set of constraints, then solve for router and host locations simultaneously. This approach improves the consistency of location estimates, reducing the error substantially for structured networks in our experiments on Abilene and Sprint. For networks with insufficient structural constraints, our techniques integrate external hints that are validated using measurements before being trusted. Together, these techniques lower the median estimation error for our university-based dataset to 67 km vs. 228 km for the best previous approach.

Low-Power 2.4-GHz Transceiver With Passive RX Front-End and 400-mV Supply

Abstract: An ultra low power 2.4-GHz transceiver targeting wireless sensor network applications is presented. The receiver front-end is fully passive, utilizing an integrated resonant matching network to achieve voltage gain and interface directly to a passive mixer. The receiver achieves a 7-dB noise figure and -7.5-dBm IIP3 while consuming 330 muW from a 400-mV supply. The binary FSK transmitter delivers 300 muW to a balanced 50-Omega load with 30% overall efficiency and 45% power amplifier (PA) efficiency. Performance of the receiver topology is analyzed and simple expressions for the gain and noise figure of both the passive mixer and matching network are derived. An analysis of passive mixer input impedance reveals the potential to reject interferers at the mixer input with characteristics similar to an extremely high-Q parallel LC filter centered at the switching frequency

A bidirectional DC–DC converter for fuel cell electric vehicle driving system

Abstract: This paper presents a power converter for a fuel cell electric vehicle driving system. A new bidirectional, isolated topology is proposed in consideration of the differing fuel cell characteristics from traditional chemical-power battery and safety requirements. The studied converter has the advantages of high efficiency, simple circuit, and low cost. The detailed design and operating principles are analyzed and described. The simulation and experimental waveforms for the proposed converter are shown to verify its feasibility.

A New Simplified Multilevel Inverter Topology for DC–AC Conversion

Abstract: Multilevel converters offer high power capability, associated with lower output harmonics and lower commutation losses. Their main disadvantage is their complexity, requiring a great number of power devices and passive components, and a rather complex control circuitry. This work reports a new multilevel inverter topology using an H-bridge output stage with a bidirectional auxiliary switch. The new topology produces a significant reduction in the number of power devices and capacitors required to implement a multilevel output. The new topology is used in the design of a five-level inverter; only five controlled switches, eight diodes, and two capacitors are required to implement the five-level inverter using the proposed topology. The new topology achieves a 37.5% reduction in the number of main power switches required (five in the new against eight in any of the other three configurations) and uses no more diodes or capacitors that the second best topology in the literature, the Asymmetric Cascade configuration. Additionally, the dedicated modulator circuit required for multilevel inverter operation is implemented using a FPGA circuit, reducing overall system cost and complexity. Theoretical predictions are validated using simulation in SPICE, and satisfactory circuit operation is proved with experimental tests performed on a laboratory prototype

A Fully Integrated 2.4-GHz IEEE 802.15.4-Compliant Transceiver for ZigBee™ Applications

Abstract: A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high sensitivity and low power consumption, and achieves -101 dBm sensitivity for 1% packet error rate. The transmitter topology is based on a PLL direct-modulation scheme. Optimizations of architecture and circuit design level in order to reduce the transceiver power consumption are described. Special attention is paid to the RF front-end design which consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm2 chip is implemented in a standard 0.18-mum CMOS technology. The transmitter delivers +3 dBm into the 100-Omega differential antenna port

Estimating topology of networks.

Abstract: We suggest a method for estimating the topology of a network based on the dynamical evolution supported on the network. Our method is robust and can be also applied when disturbances and/or modeling errors are presented. Several examples with networks of phase oscillators, pulse-coupled Hindmarch-Rose neurons, and Lorenz oscillators are provided to illustrate our approach.

Design of loosely coupled inductive power transfer systems

Abstract: The model of inductive power system is set up,and how to choose the compensation topology and resonant frequency is analyzed.According to the analysis result,the model of inductive power system is set up,and the impact of the power transfer due to the variety of load is analyzed.

Design-oriented steady-state analysis of LLC resonant converters based on FHA

Abstract: The aim of this paper is to present a comprehensive design methodology for an LLC resonant converter, based on a detailed quantitative analysis of the steady-state operation of the circuit. This analysis follows the first harmonic approximation (FHA) approach, which tremendously simplifies the system model, leading to a linear circuit, which can be dealt with through the classical complex AC-circuit analysis. Two of the major benefits of the LLC resonant topology are the ability of the power MOSFETs and secondary rectifiers to be soft-switched and the capability of operating down to zero load. The design-oriented steady-state analysis presented in this paper addresses these two constraints quantitatively, allowing the designer to derive the circuit parameters which not only fulfil input voltage and output power specification data but also soft-switching and no-load operation constraints

A Multilevel Modular Capacitor Clamped DC-DC Converter

Abstract: A novel topology of multilevel modular capacitor clamped dc-dc converter (MMCCC) will be presented in this paper. In contrast to the conventional flying capacitor multilevel dc-dc converter (FCMDC), this new topology is completely modular and requires a simpler gate drive circuit. Moreover, the new topology has many advantageous features such as high frequency operation capability, low input/output current ripple, lower on-state voltage drop, and bi-directional power flow management. This paper discusses the construction and operation of the new converter along with a comparison with a conventional converter. Finally, the simulation and experimental results validate the concept of this new topology.

A high-performance axial-field magnetic gear

Abstract: The paper describes an axial-field topology of magnetic gear, which is particularly suitable for applications which require a hermetic isolation between the input and output shafts, such as pumps for use in the chemical/pharmaceutical, food, and aerospace industries. It is shown that a torque density in excess of 70kNm∕m3 can be achieved, and that the axial forces, which are exerted on the high-speed and low-speed rotors, are relatively low.

A compact size coupling controllable filter with separate electric and magnetic coupling paths

Abstract: This paper presents the characteristics of a miniaturized microstrip filter, which has two separate coupling paths: electric coupling path and magnetic coupling path between two resonators. Either magnetic coupling or electric coupling in two paths can be dominant in the total coupling coefficient of the inter-stage resonators with the similar configuration, but different positions of transmission zero points (ZPs). Based on the proposed filter topology, second- and fourth-order filters have been designed and fabricated for the first time. Advantages of using this type of filter are not only its low insertion loss and much more compact size, but also its controllable transmission ZPs.

Deterministic boundary recognition and topology extraction for large sensor networks

Abstract: We present a new framework for the crucial challenge of self-organization of a large sensor network. The basic scenario can be described as follows: Given a large swarm of immobile sensor nodes that have been scattered in a polygonal region, such as a street network. Nodes have no knowledge of size or shape of the environment or the position of other nodes. Moreover, they have no way of measuring coordinates, geometric distances to other nodes, or their direction. Their only way of interacting with other nodes is to send or to receive messages from any node that is within communication range. The objective is to develop algorithms and protocols that allow self-organization of the swarm into large-scale structures that reflect the structure of the street network, setting the stage for global routing, tracking and guiding algorithms.Our algorithms work in two stages: boundary recognition and topology extraction. All steps are strictly deterministic, yield fast distributed algorithms, and make no assumption on the distribution of nodes in the environment, other than sufficient density.

Boost current multilevel inverter and its application on single-phase grid-connected photovoltaic systems

Abstract: This work presents a novel current multilevel (CML) inverter topology, named boost CML inverter, and its application on energy processing of single-phase grid-connected photovoltaic (PV) systems. The structure allows a high power factor operation of a PV system, injecting a quasi-sinusoidal current into the grid, with virtually no displacement in relation to the line voltage at the point of common coupling among the PV system and the loads. The major appeals of using the CML technique are the balanced current sharing among semiconductor switches and the decrease of the current slope in the circuit devices, with a consequent reduction of conducted and radiated electromagnetic interference (EMI). The CML technique also allows adapting or minimizing current waveforms harmonic content. System description, mathematical approach, and design guidelines are presented, providing an overview of the new topology. In order to validate the proposed concepts, experimental measurements, made in a small-scale laboratory prototype, are also presented. The obtained results evidence the feasibility of the application of this new topology on singlephase grid-connected PV systems.

Soft-Error-Rate-Analysis (SERA) Methodology

Abstract: We present a soft-error-rate analysis (SERA) methodology for combinational and memory circuits. SERA is based on a modeling and analysis approach that employs a judicious mix of probability theory, circuit simulation, graph theory, and fault simulation. SERA achieves five orders of magnitude speedup over Monte Carlo-based simulation approaches with less than 5% error. Dependence of the soft-error rate (SER) of combinational logic circuits on a supply voltage, clock period, latching window, circuit topology, and input vector is explicitly captured and studied for a typical 0.18-mum CMOS process. Results show that the SER of logic is a much stronger function of timing parameters than the supply voltage. Also, an SER peaking phenomenon in multipliers is observed where the center bits have an SER that are orders of magnitude greater than those of the LSBs and the MSBs. An increase of up to 25% in the SER for multiplier circuits of various sizes has been observed as technology scales from 0.18 to 0.13 mum

An enhanced genetic algorithm for structural topology optimization

Abstract: Genetic algorithms (GAs) have become a popular optimization tool for many areas of research and topology optimization an effective design tool for obtaining efficient and lighter structures. In this paper, a versatile, robust and enhanced GA is proposed for structural topology optimization by using problem-specific knowledge. The original discrete black-and-white (0–1) problem is directly solved by using a bit-array representation method. To address the related pronounced connectivity issue effectively, the four-neighbourhood connectivity is used to suppress the occurrence of checkerboard patterns. A simpler version of the perimeter control approach is developed to obtain a well-posed problem and the total number of hinges of each individual is explicitly penalized to achieve a hinge-free design. To handle the problem of representation degeneracy effectively, a recessive gene technique is applied to viable topologies while unusable topologies are penalized in a hierarchical manner. An efficient FEM-based function evaluation method is developed to reduce the computational cost. A dynamic penalty method is presented for the GA to convert the constrained optimization problem into an unconstrained problem without the possible degeneracy. With all these enhancements and appropriate choice of the GA operators, the present GA can achieve significant improvements in evolving into near-optimum solutions and viable topologies with checkerboard free, mesh independent and hinge-free characteristics. Numerical results show that the present GA can be more efficient and robust than the conventional GAs in solving the structural topology optimization problems of minimum compliance design, minimum weight design and optimal compliant mechanisms design. It is suggested that the present enhanced GA using problem-specific knowledge can be a powerful global search tool for structural topology optimization. Copyright © 2005 John Wiley & Sons, Ltd.

Synthesis of dual-band bandpass filters using successive frequency transformations and circuit conversions

Abstract: A novel method is proposed to synthesize dual-band bandpass filters (BPFs) from a prototype low-pass filter. By implementing successive frequency transformations and circuit conversions, a new filter topology is obtained which consists of only admittance inverters and series resonators, and is thereby easy to be realized by using conventional distributed elements. A dual-band BPF with center frequencies of 1.8GHz and 2.4GHz is designed and fabricated using microstrip lines and stubs. The simulated and measured results show a good agreement and validate the proposed theory.

Research on Hybrid-Clamped Multilevel-Inverter Topologies

Abstract: The concept of hybrid clamped is proposed in multilevel-inverter topologies, and a hybrid-clamped multilevel-inverter topology comprising active and passive clamping devices is presented in this paper. In this topology, the dc-link capacitor voltages can be balanced without additional circuitry or separated dc voltage sources, regardless of load characteristics. It can be used in real and reactive power conversion applications. The topology structure, operating principle, and self-voltage balancing ability are analyzed. In addition, the validity is confirmed by simulations and experiments based on a five-level inverter. Finally, the functions of different clamping devices are compared

A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider

Abstract: A new injection-locked frequency divider (ILFD) topology is proposed for divide-by-odd-number operation. An 18 GHz divide-by-3 prototype is implemented using 0.18mum standard digital CMOS with low-resistivity substrate. It achieves 1 GHz locking range with 3.4dBm injection power, which increases to 3.2GHz with built-in tuning. The phase noise is close to theoretical value of 9.5dB down from input

A level-crossing flash asynchronous analog-to-digital converter

Abstract: Distributed sensor networks, human body implants, and hand-held electronics have tight energy budgets that necessitate low power circuits. Most of these devices include an analog-to-digital converter (ADC) to process analog signals from the physical world. We describe a new topology for an asynchronous analog-to-digital converter, dubbed LCF-ADC, that has several major advantages over previously-designed ADCs, including reduced energy consumption and/or a simplification of the analog circuits required for its implementation. In this paper we describe the design of the LCF-ADC architecture, and present simulation results that show low power consumption. We discuss both theoretical considerations that determine the performance of our ADC as well as a proposed implementation. Comparisons with previously designed asynchronous analog-to-digital converters show the benefits of the LCF-ADC architecture. In 180 nm CMOS, our ADC is expected to consume 43 /spl mu/W at 160 kHz, and 438 /spl mu/W at 5 MHz.

A Multilevel Inverter Topology for Inductively Coupled Power Transfer

Abstract: This paper describes a multilevel inverter that can synthesize quantized approximations of arbitrary ac waveforms. This converter could be used to deliver power over multiple frequencies simultaneously. Unlike traditional multilevel inverters, this topology does not require an external voltage balancing circuit, a complicated control scheme, or isolated dc sources to maintain its voltage levels while delivering sustained real power. In this paper, we use this circuit for heating frequency selectable induction targets designed to stimulate temperature sensitive polymer gel actuators. For this application our multilevel inverter offers higher efficiency than a pulse width modulated full-bridge inverter (a more conventional power supply solution) at comparable levels of total harmonic distortion

A GaN HEMT Class F Amplifier at 2 GHz with > 80 % PAE

Abstract: A Class F amplifier has been designed, fabricated, and tested using a GaN HEMT transistor and hybrid printed circuit board (PCB) packaging. The amplifier has a peak power-added efficiency (PAE) of 85% with an output power of 16.5 W. A gate-connected field-plated and a source-connected field-plated device of the same size and layout were measured in this topology. An output power and drain efficiency tradeoff, dependant on the drain impedance at the fundamental frequency due to the on-state resistance, is explored. A comparison between Class F and Inverse F, given particular operating conditions for this device, is made.

High-efficiency Voltage-clamped DC-DC converter with reduced reverse-recovery current and switch-Voltage stress

Abstract: This paper investigates a high-efficiency clamped-voltage dc-dc converter with reduced reverse-recovery current and switch-voltage stress. In the circuit topology, it is designed by way of the combination of inductor and transformer to increase the corresponding voltage gain. Moreover, one additional inductor provides the reverse-current path of the transformer to enhance the utility rate of magnetic core. In addition, the voltage-clamped technology is used to reduce the switch-voltage stress so that it can select the Schottky diode in the output terminal for alleviating the reverse-recovery current and decreasing the switching and conduction losses. Furthermore, the closed-loop control methodology is utilized in the proposed scheme to overcome the voltage-drift problem of power source under the variation of loads. Thus, the proposed converter topology has a favorable voltage-clamped effect and superior conversion efficiency. Some experimental results via an example of a proton-exchange-membrane fuel cell (PEMFC) power source with a 250-W nominal rating are given to demonstrate the effectiveness of the proposed power-conversion strategy.

Topology and dimensional synthesis of compliant mechanisms using discrete optimization

Abstract: A unified approach to topology and dimensional synthesis of compliant mechanisms is presented in this paper as a discrete optimization problem employing both discrete (topology) and continuous (size) variables. The synthesis scheme features a design parameterization method that treats load paths as discrete design variables to represent various topologies, thereby ensuring structural connectivity among the input, output, and ground supports. The load path synthesis approach overcomes certain design issues, such as "gray areas" and disconnected structures, inherent in previous design schemes. Additionally, multiple gradations of structural resolution and a variety of configurations can be generated without increasing the number of design variables. By treating topology synthesis as a discrete optimization problem, the synthesis approach is incorporated in a genetic algorithm to search for feasible topologies for single-input single-output compliant mechanisms. Two design examples, commonly seen in the compliant mechanisms literature, are included to illustrate the synthesis procedure and to benchmark the performance. The results show that the load path synthesis approach can effectively generate well-connected compliant mechanism designs that are free of gray areas.

Design of Flux-Switching Permanent Magnet Machine Considering the Limitation of Inverter and Flux-Weakening Capability

Abstract: In this paper, a general design procedure for the flux-switching permanent magnet (FSPM) machine with different topologies is proposed. Firstly, a 3-phase 12-stator-tooth/10-rotor-pole topology is introduced and its operation principle is described. Then, the basic design method, including determination of the stator, rotor and magnet dimensions, is proposed under the constraints of some dimensions and electrical parameters. The winding turns are obtained by iteratively solving the base-speed and current equations simultaneously. The influence of current density and slot packing factor on the flux-weakening capability is investigated in the design stage to satisfy the torque and wide-speed operation requirement. Further, the output power equation, consequently, the sizing equation is derived for determining the initial dimensions of a FSPM machine, in which the traditional D2 sil a is replaced by D2 sola. Hence, the power density of different topologies can be compared directly by the equation. It reveals that the 3-phase 12/10-pole topology can offer higher power and power density than those of the 2-phase 8/6-pole machine by ~11% in theory under the same conditions. The experiments on the prototype motor verify the performance predictions

A Survey on Topology issues in Wireless Sensor Network.

Abstract: Topology issues have received more and more attentions in Wireless Sensor Networks (WSN). While WSN applications are normally optimized by the given underlying network topology, another trend is to optimize WSN by means of topology control. A number of approaches have been invested in this area, such as topology directed routing, cooperating schemes, sensor coverage based topology control and network connectivity based topology control. Most of the schemes have proven to be able to provide a better network monitoring and communication performance with prolonged system lifetime. In this survey paper, we provide a full view of the studies in this area. By summarizing previous achievements and analyzing existed problems, we also point out possible research directions for future work .

Security for Pervasive Health Monitoring Sensor Applications

Abstract: Maintaining security of wearable networked health monitoring sensors (body sensor networks (BSN)) is very important for the acceptance and long term viability of the technology. Sensors in BSNs organize themselves into different topologies for efficiency purpose. Securing these topology formation process is of prime importance. In this paper we present two schemes which rely on the novel technique of using physiological values from the wearer's body for securing a cluster topology formation. Traditional schemes for cluster (one of the most commonly used topology) formation were not designed with security in mind and are susceptible to security flaws. The schemes proposed here not only solve the secure cluster formation problem but also do so efficiently by eliminating all key distribution overheads. We analyzed the security of the protocols and tested their accuracy on a prototype implementation developed using Mica2 motes.

Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

Abstract: Contents List of Tables List of Figures Symbols and Abbreviations Physical Definitions 1 Introduction 1.1 Motivation 1.2 Outline of the work 2 ADCs in Deep-Submicron CMOS Technologies 2.1 Introduction 2.2 Scaling-Down of CMOS Technologies 2.2.1 Driving Force of the CMOS Scaling-Down 2.2.2 Moving Into Deep-Submicron CMOS Technologies 2.3 Impact of Moving Into Deep-Submicron CMOS to Analog Circuits 2.3.1 Decreased Supply Voltage 2.3.2 Impact on Transistor Intrinsic Gain 2.3.3 Impact on Device Matching 2.3.4 Impact on Device Noise 2.4 ADCs In Deep-Submicron CMOS 2.4.1 Decreased Signal Swing 2.4.2 Degraded Transistor Characteristics 2.4.3 Distortion 2.4.4 Switch Driving 2.4.5 Improved Device Matching 2.4.6 Digital Circuits Advantages 2.5 Conclusion 3 Principle of sigma-delta ADC 3.1 Introduction 3.2 Basic Analog to Digital Conversion 3.3 Oversampling and Noise Shaping 3.3.1 Oversampling 3.3.2 Noise Shaping 3.3.3 sigma-delta modulator 3.3.4 PerformanceMetrics for the sigma-delta ADC 3.4 Traditional sigma-delta ADC Topology 3.4.1 Single-Loop Single-Bit sigma-delta Modulators 3.4.2 Single-Loop Multibit sigma-delta Modulators 3.4.3 Cascaded sigma-delta Modulators 3.5 Conclusion 4 Low-Power Low-Voltage sigma-delta ADC Design in Deep-Submicron CMOS: Circuit Level Approach 4.1 Introduction 4.2 Low-Voltage Low-Power OTA Design 4.2.1 Gain Enhanced Current Mirror OTA Design 4.2.2 A Test Gain-Enhanced Current Mirror OTA 4.2.3 Implementation and Measurement Results 4.2.4 Two-Stage OTA Design 4.3 Low-Voltage Low-Power sigma-delta ADC Design 4.3.1 Impact of Circuit Nonidealities to sigma-delta ADC Performance 4.3.2 Modulator Topology Selection 4.3.3 OTA Topology Selection 4.3.4 Transistor Biasing 4.3.5 Scaling of Integrators 4.4 A 1-V 140- Wsigma-delta modulator in 90-nm CMOS 4.4.1 Building Block Circuits Design 4.4.2 Implementation 4.4.3 Measurement Results 4.5 Measurements on PSRR and Low-Frequency Noise Floor 4.5.1 Introduction of PSRR 4.5.2 PSRR Measurement Setup 4.5.3 PSRR Measurement Results 4.5.4 Measurement on Low-Frequency Noise Floor 4.6 Conclusion 5 Low-Power Low-Voltage sigma-delta ADC Design in Deep-Submicron CMOS: System Level Approach 5.1 Introduction 5.2 The Full Feedforward sigma-delta ADC Topology 5.2.1 Single-Loop Single-Bit Full Feedforward sigma-delta Modulators 5.2.2 Single-Loop Multibit Full Feedforward sigma-delta Modulators 5.2.3 Cascaded Full Feedforward sigma-delta Modulators 5.3 Linearity Analysis of sigma-delta ADC 5.3.1 Non-LinearitiesModeling in sigma-delta ADC 5.3.2 Non-Linear OTA Gain Modeling in sigma-delta ADC 5.3.3 Linearity Performance Comparison 5.4 Circuit Implementation of the Full Feedforward sigma-delta Modulator 5.5 A 1.8-V 2-MS/s sigma-delta Modulator in 0.18- m CMOS 5.5.1 Implementation 5.5.2 Measurement results 5.6 A 1-V 1-MS/s sigma-delta Modulator in 0.13- m CMOS 5.6.1 Implementation 5.6.2 Measurement Results 5.7 Multibit Full Feedforward sigma-delta Modulator Design 5.7.1 Optimized Loop Coefficients 5.7.2 Circuit Implementation 5.8 Conclusion 6 Flash ADC Design in Deep-Submicron CMOS 6.1 Introduction 6.2 Mismatch Study in Deep-Submicron CMOS Technologies 6.2.1 Mismatch of Components

Topology control in ad hoc wireless networks using cooperative communication

Abstract: In this paper, we address the Topology control with Cooperative Communication (TCC) problem in ad hoc wireless networks. Cooperative communication is a novel model introduced recently that allows combining partial messages to decode a complete message. The objective of the TCC problem is to obtain a strongly-connected topology with minimum total energy consumption. We show that the TCC problem is NIP-complete and design two distributed and localized algorithms to be used by the nodes to set up their communication ranges. Both algorithms can be applied on top of any symmetric, strongly-connected topology to reduce total power consumption. The first algorithm uses a distributed decision process at each node that makes use of only 2-hop neighborhood information. The second algorithm sets up the transmission ranges of nodes iteratively, over a maximum of six steps, using only 1-hop neighborhood information. We analyze the performance of our approaches through extensive simulation.