scispace - formally typeset
Search or ask a question
Topic

Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.


Papers
More filters
Journal ArticleDOI
TL;DR: It is shown that the analytical models match the simulation results very well in the case of the centralized switch and the mesh network, and wavelength translation can significantly improve the performance of a large mesh-torus network.
Abstract: In this paper, we study the benefits of wavelength translation in all-optical networks providing clear channel circuit-switching among users. We first establish approximate analytical models for a static-routing circuit-switched network with an arbitrary topology, both with and without wavelength translation. We then study the performance of the nonblocking centralized switch, the mesh-torus network and the ring network, using the analytical models and simulation results. It is shown that the analytical models match the simulation results very well in the case of the centralized switch and the mesh network. The results of our study also show that the benefits of wavelength translation are modest for the centralized switch and the ring network. On the other hand, the results show that wavelength translation can significantly improve the performance of a large mesh-torus network.

387 citations

Journal ArticleDOI
TL;DR: A new power multilevel converter topology that is very competitive compared to the existing ones that consists of packed U cells (PUC), which offers high-energy conversion quality using a small number of capacitors and power devices and consequently, has a very low production cost.
Abstract: In this paper, authors propose a new power multilevel converter topology that is very competitive compared to the existing ones. It consists of packed U cells (PUC). Each U cell consists of an arrangement of two power switches and one capacitor. It offers high-energy conversion quality using a small number of capacitors and power devices and consequently, has a very low production cost. An averaged model of the topology is detailed. The operating principle of the transformerless seven-level inverter is analyzed and detailed. The multilevel sinusoidal modulation has been adapted for use with the PUC-based structure. The control strategy has been designed to reduce the harmonic contents of the load voltage. With such converters, filters' rating is considerably reduced. A comparative study is performed to highlight the advantages of the new packed U cells topology. The operation of the proposed converter topology has been verified through simulation. Experimental validation was performed using DS1103 DSP of dSpace.

383 citations

Journal ArticleDOI
TL;DR: Simulation and experimental results show that all three controllers meet LVRT requirements, although different system performance is found for each control approach, and controller selection depends on the system constraints and the type of preferred performance features.
Abstract: Low-voltage ride-through (LVRT) requirements demand wind-power plants to remain connected to the network in presence of grid-voltage dips. Most dips present positive-, negative-, and zero-sequence components. Hence, regulators based on symmetrical components are well suited to control grid-connected converters. A neutral-point-clamped topology has been considered as an active front end of a distributed power-generation system, following the trend of increasing power and voltage levels in wind-power systems. Three different current controllers based on symmetrical components and linear quadratic regulator have been considered. The performance of each controller is evaluated on LVRT requirement fulfillment, grid-current balancing, maximum grid-current value control, and oscillating power flow. Simulation and experimental results show that all three controllers meet LVRT requirements, although different system performance is found for each control approach. Therefore, controller selection depends on the system constraints and the type of preferred performance features.

367 citations

Journal ArticleDOI
TL;DR: This paper analyzes the design of the passive components and gives a practical and low-cost solution for the minimization of the circulation currents between the inverters, by using common-mode coils.
Abstract: In this paper, an interleaved active-power-filter concept with reduced size of passive components is discussed. The topology is composed of two pulsewidth-modulation interleaved voltage-source inverters connected together on the ac line and sharing the same dc-link capacitor. The advantages of the proposed approach are as follows: 1. significant reduction in the linkage inductors' size by decreasing the line-current ripple due to the interleaving; 2. reduction of the switching stress in the dc-link capacitor, due to the shared connection; and 3. more accurate compensation for high-power applications, because the power sharing allows one to use a higher switching frequency in each inverter. This paper analyzes the design of the passive components and gives a practical and low-cost solution for the minimization of the circulation currents between the inverters, by using common-mode coils. Several simulation results are discussed, and experimental results with a three-phase 10-kVA 400-V unit are obtained to validate the theoretical analysis.

364 citations

Journal ArticleDOI
TL;DR: Applications of the topology optimization method to the design of macro structures for minimum compliance and micro compliant mechanisms show that the method provides manufacturing tolerant designs with little decrease in performance.
Abstract: In this paper we present an extension of the topology optimization method to include uncertainties during the fabrication of macro, micro and nano structures. More specifically, we consider devices that are manufactured using processes which may result in (uniformly) too thin (eroded) or too thick (dilated) structures compared to the intended topology. Examples are MEMS devices manufactured using etching processes, nano-devices manufactured using e-beam lithography or laser micro-machining and macro structures manufactured using milling processes. In the suggested robust topology optimization approach, under- and over-etching is modelled by image processing-based “erode” and “dilate” operators and the optimization problem is formulated as a worst case design problem. Applications of the method to the design of macro structures for minimum compliance and micro compliant mechanisms show that the method provides manufacturing tolerant designs with little decrease in performance. As a positive side effect the robust design formulation also eliminates the longstanding problem of one-node connected hinges in compliant mechanism design using topology optimization.

364 citations


Network Information
Related Topics (5)
Capacitor
166.6K papers, 1.4M citations
90% related
Voltage
296.3K papers, 1.7M citations
88% related
CMOS
81.3K papers, 1.1M citations
86% related
Integrated circuit
82.7K papers, 1M citations
85% related
Amplifier
163.9K papers, 1.3M citations
83% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
20241
20233,701
20227,927
20212,733
20202,663
20192,742