Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

A hybrid wind-solar energy system: A new rectifier stage topology

Abstract: Environmentally friendly solutions are becoming more prominent than ever as a result of concern regarding the state of our deteriorating planet. This paper presents a new system configuration of the front-end rectifier stage for a hybrid wind/photovoltaic energy system. This configuration allows the two sources to supply the load separately or simultaneously depending on the availability of the energy sources. The inherent nature of this Cuk-SEPIC fused converter, additional input filters are not necessary to filter out high frequency harmonics. Harmonic content is detrimental for the generator lifespan, heating issues, and efficiency. The fused multi-input rectifier stage also allows Maximum Power Point Tracking (MPPT) to be used to extract maximum power from the wind and sun when it is available. An adaptive MPPT algorithm will be used for the wind system and a standard perturb and observe method will be used for the PV system. Operational analysis of the proposed system will be discussed in this paper. Simulation results are given to highlight the merits of the proposed circuit.

Network Reconstruction from Random Phase Resetting

Abstract: We propose a novel method of reconstructing the topology and interaction functions for a general oscillator network. An ensemble of initial phases and the corresponding instantaneous frequencies is constructed by repeating random phase resets of the system dynamics. The desired details of network structure are then revealed by appropriately averaging over the ensemble. The method is applicable for a wide class of networks with arbitrary emergent dynamics, including full synchrony.

Stochastic resonance in hybrid scale-free neuronal networks

Abstract: We study the phenomenon of stochastic resonance in a system of coupled neurons that are globally excited by a weak periodic input signal. We make the realistic assumption that the chemical and electrical synapses interact in the same neuronal network, hence constituting a hybrid network. By considering a hybrid coupling scheme embedded in the scale-free topology, we show that the electrical synapses are more efficient than chemical synapses in promoting the best correlation between the weak input signal and the response of the system. We also demonstrate that the average degree of neurons within the hybrid scale-free network significantly influences the optimal amount of noise for the occurrence of stochastic resonance, indicating that there also exists an optimal topology for the amplification of the response to the weak input signal. Lastly, we verify that the presented results are robust to variations of the system size.

A versatile power converter for high-frequency link systems

Abstract: A single-phase high-frequency link appears to be an attractive alternative to the DC link commonly used in power conversion systems. The authors propose a power converter suitable for one-step conversion of the single-phase high-frequency link voltage to the three-phase low-frequency voltages typically required for interfacing with system sources and loads. The converter utilizes zero voltage switching principles to minimize switching losses and uses an easy-to-implement technique of pulse density modulation for the control of the amplitude, frequency, and waveshape of the synthesized low-frequency signals. Adaptation of the proposed topology for power conversion to single-phase AC and DC voltage or current outputs is shown to be straightforward. The feasibility of the proposed power circuit and the control technique have been experimentally verified. >

Gated clock routing for low-power microprocessor design

Abstract: This paper presents a zero-skew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the switched capacitance of the clock tree. We construct a clock-tree topology based on the locations and the activation frequencies of the modules, while the locations of the internal nodes of the clock tree (and, hence, the masking gates) are determined using a dynamic programming approach followed by a gate reduction heuristic. This work assumes that the gates are turned on/off by a centralized controller. Therefore, the additional power and routing area incurred by the controller and the gate control signal routing are examined. Various tradeoffs between power and area for different design options and module activities are discussed and detailed experimental results are presented. Finally, good design practices for implementing the gated clocks are suggested.