Topic
Topology (electrical circuits)
About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.
Papers published on a yearly basis
Papers
More filters
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07 Jun 1998TL;DR: In this article, a synthesis procedure for multiple coupled resonator filters with general topology and general response is described, where the optimization is performed directly on the element values of the coupling matrix.
Abstract: A synthesis procedure, using optimization, for multiple coupled resonator filters having general topology and general response is described. The error function for the optimization is based on the values of the characteristic function at its zeros and poles. The optimization is performed directly on the element values of the coupling matrix. Convergence of the optimization is extremely fast and nearly independent of the starting coupling matrix. Examples of the design of practical filters with symmetric or asymmetric responses and topology are presented.
105 citations
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26 Jul 2015TL;DR: In this paper, the authors compared how a dc fault affects a multi-terminal dc (MTdc) network depending on the HVDC transmission system topology and proposed a six-step methodology for the selection of the necessary dc fault protection measures.
Abstract: This paper compares how a dc fault affects a multi-terminal dc (MTdc) network depending on the HVDC transmission system topology To this end, a six-step methodology is proposed for the selection of the necessary dc fault protection measures The network consists of four voltage-source converters converters radially connected The converters natural fault response to a dc fault for the different topologies is studied using dynamic simulation models For clearing of the dc faults, four different dc breaker technologies are compared based on their fault interruption time, together with a current direction fault detection method If necessary, the converters are reinforced with limiting reactors to decrease the peak value and rate of rise of the fault currents providing sufficient time for the breakers to isolate the fault without interrupting the MTdc network operation The study shows that the symmetric monopolar topology is least affected by dc contingencies Considering bipolar topologies, the bipolar with metallic return exhibits better fault response compared to the one with ground return Topologies with ground or metallic return require full semiconductor or hybrid breakers with reactors to successfully isolate a dc fault
105 citations
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TL;DR: In this paper, a hysteresis current control technique for a single-phase five-level inverter with flying-capacitor topology is proposed, which is suitable for handling a large number of switches and implementation of state transitions.
Abstract: In most high-performance applications of voltage source pulse-width modulation inverters, current control is an essential part of the overall control system. In this paper, a hysteresis current control technique for a single-phase five-level inverter with flying-capacitor topology is proposed. Logic controls and a programmable logic device are suitable for handling a large number of switches and implementation of state transitions. This method also considers how to improve unbalanced voltages of capacitors using voltage vectors in order to minimize switching losses. The simulation and experimental results describe and verify the current control technique for the inverter.
105 citations
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TL;DR: This paper investigates the use of a three-leg voltage source inverter topology for supplying two-phase induction motors and presents two pulse width modulation techniques for voltage control and a quasi time-invariant model to describe an unbalanced two- phase machine.
Abstract: This paper investigates the use of a three-leg voltage source inverter topology for supplying two-phase induction motors. The paper also presents two pulse width modulation techniques for voltage control and a quasi time-invariant model to describe an unbalanced two-phase machine. The correctness of the proposed drive system was demonstrated through experimental results obtained with a laboratory prototype.
105 citations
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01 Nov 2006TL;DR: A comparison between Class F and Inverse F, given particular operating conditions for this device, is made and an output power and drain efficiency tradeoff is explored.
Abstract: A Class F amplifier has been designed, fabricated, and tested using a GaN HEMT transistor and hybrid printed circuit board (PCB) packaging. The amplifier has a peak power-added efficiency (PAE) of 85% with an output power of 16.5 W. A gate-connected field-plated and a source-connected field-plated device of the same size and layout were measured in this topology. An output power and drain efficiency tradeoff, dependant on the drain impedance at the fundamental frequency due to the on-state resistance, is explored. A comparison between Class F and Inverse F, given particular operating conditions for this device, is made.
105 citations