Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

Batch transfer system and method for high performance graphic display of network topology

Abstract: Discovery/layout software (101) configures a general purpose computer system to act as a management station (100') using the industry standard SNMP protocol. The discovery/layout software (101) has a discovery mechanism (302) and a layout mechanism (304) which, in combination, permit the discovery/layout software (101) to provide various submaps (202-210) on demand to a display (108). The submaps (202-210) are directed to various hierarchical views of the network (118). The discovery mechanism (302) monitors and discovers the device configuration on the network (118) and maintains a topology data base (314) indicative thereof. A layout mechanism (304) has a translator (318) which converts the topology data from the topology data base (314) to map data, which is maintained in a map data base (326). Significantly, topology data is received by the translator (318) in a batch and, in addition, map data is transferred from the translator (318) in a batch so that context switching involving the change of control over the processor (102) and operating system (122) is minimized and the performance of the management station (100') is significantly enhanced.

Improved hypercube topology for multiprocessor computer systems

Abstract: A hypercube system which has been modified by adding additional communication links between the most distant nodes of a classic hypercube topology is described herein. This improvement in a hypercube topology is termed as a Modified Hypercube topology. Such a topology contains extra links which connects a node to another node in the topology which requires the greatest number of nodal hops over the shortest path. Also stated another way, that node having the greatest number of singly traversed or hopped nodes along the shortest path from an originating node to that node makes that node the most distant processor node. If hamming were to be implemented in the system, there is added an extra link between two nodes having the greatest hamming distance. Such a system makes a technological trade off to reduce the diameter of a classic hypercube at the cost of incrementally increasing the number of I/O ports at each node. This trade off has been recognized in the industry as advantageous since a great gain in performance is achieved n exchange for an incremental impact to the hardware. Clearly the performance advantages of the present invention grows as the number of nodes in the hypercube grows and the maximum distance between nodes increases.

Dynamic network topology determination

Abstract: A system and method for dynamically determining the physical connection topology between diverse network elements (DNEs) within a communication network. Each DNE is audited on a periodic basis to determine the arrangement, configuration, cross-connection, and alarm status of each communication port within each DNE in the communications network. A topology database is maintained with such baseline information. Each DNE is configured with at least one mismatched port. Mismatched ports are cross-connected with communication ports within DNEs so that signal mismatch alarms are generated by communication ports coupled with the mismatched ports in other DNEs. Signal mismatch alarms are collected and processed so that connectivity status may be derived based on the baseline data, expected alarms, and the receipt of such alarms or lack thereof. A topology database is continuously updated to reflect such derived information.

Single-phase AC/AC converter based on quasi-Z-source topology

Abstract: This paper deals with a new family of quasi-Z-source converters applying to AC/AC power conversion called single-phase quasi-Z-source AC/AC converter (qZSAC). The proposed qZSAC inherits all the advantages of the traditional single-phase Z-source AC/AC converter (ZSAC), which can realize buck-boost, reversing or maintaining phase angle. In addition, the proposed qZSAC has the unique features; namely that the input voltage and output voltage is sharing the same ground; the operation is in continuous current mode (CCM). Compared to the conventional ZSAC, the proposed qZSAC has a lower harmonic distortion input current and a higher efficiency. The proposed qZSAC can control to shape the input current to be sinusoidal and in phase with the input voltage. The operating principles of the proposed qZSAC are described, and a circuit analysis is provided. Simulation results are shown in comparison to that of the conventional SZAC. Experimentation is implemented to verify the operational concept.

A multistage amplifier technique with embedded frequency compensation

Abstract: A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-/spl mu/m n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V//spl mu/s average slew rate with 40 pF load.