Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

Application of Topology, Sizing and Shape Optimization Methods to Optimal Design of Aircraft Components

Abstract: Topology optimisation has for a considerable time been applied successfully in the automotive industry, but still has not become a mainstream technology for the design of aircraft components. The explanation for this is partly to be sought in the larger problem sizes and in the often quite complicated support and loading conditions for aircraft components. Also, aircraft components are often stability designs and the compliance based topology optimisation method still lacks the ability to deal with any buckling criteria. The present paper considers the use of the compliance formulated topology optimisation method and detailed sizing/shape optimisation methods to the design of aircraft components but also discusses the difficulties in obtaining correct loading and boundary conditions for finite element based analysis/optimisation of components that are integral parts of a larger structure.

Experimental Validation of High-Voltage-Ratio Low-Input-Current-Ripple Converters for Hybrid Fuel Cell Supercapacitor Systems

Abstract: Electric vehicle technology has been adopting fuel cells (FCs) for hybrid applications over the past few years. Therefore, the development of advanced power electronic systems for the integration of fuel cells with on-board energy management is fundamental for achieving high-performance systems. An FC for vehicular applications is usually a low-voltage current-source like device that produces electricity and heat directly from input hydrogen and oxygen. Most often, it is required that the FCs be stacked for high-voltage dc-link in order to supply the input power for the drivetrain and electric motor drive system. The FC has a nonlinear nature, and it must be controlled to operate in the high-efficiency operating range. Hybrid electric vehicles have physical constraints such as volume and weight under limited cost and expected lifetime. There is a need for high-voltage input/output ratio of dc-dc boost converters to be connected between the FC to the motor drive dc-link. In addition, it is necessary to have low input ripple at the dc-dc boost converter in order to maximize the FC lifetime, and the traditional dc-dc boost converter topologies have poor performance on these specifications. This paper proposes a new dc-dc converter family of topologies aimed at improving the application to electric vehicle power control. This family is defined as floating-interleaving boost converters (FIBCs). The paper will thoroughly show analysis and experimental verification of FIBC's, and they will be compared with conventional boost converter characteristics. The paper supports how performance figures related to the passive components, i.e., the inductor and capacitor, will have better volume and weight, extremely low input current ripple, and improved efficiency and transfer ratio. The analysis presented in this paper shows how to choose the most suitable topology in order to achieve the desired specifications. The selected topology is fully validated experimentally using advanced nonlinear sliding mode control, which has the additional feature of operating even in faulty conditions.

Data center network architecture

Abstract: Data center network architectures that can reduce the cost and complexity of data center networks. The data center network architectures can employ optical network topologies and optical nodes to efficiently allocate bandwidth within the data center networks, while reducing the physical interconnectivity requirements of the data center networks. The data center network architectures also allow computing resources within data center networks to be controlled and provisioned based at least in part on a combined network topology and application component topology, thereby enhancing overall application program performance.

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Abstract: Automatic transistor sizing is a challenging problem in circuit design due to the large design space, complex performance tradeoffs, and fast technology advancements. Although there have been plenty of work on transistor sizing targeting on one circuit, limited research has been done on transferring the knowledge from one circuit to another to reduce the re-design overhead. In this paper, we present GCN-RL Circuit Designer, leveraging reinforcement learning (RL) to transfer the knowledge between different technology nodes and topologies. Moreover, inspired by the simple fact that circuit is a graph, we learn on the circuit topology representation with graph convolutional neural networks (GCN). The GCN-RL agent extracts features of the topology graph whose vertices are transistors, edges are wires. Our learning-based optimization consistently achieves the highest Figures of Merit (FoM) on four different circuits compared with conventional black box optimization methods (Bayesian Optimization, Evolutionary Algorithms), random search and human expert designs. Experiments on transfer learning between five technology nodes and two circuit topologies demonstrate that RL with transfer learning can achieve much higher FoMs than methods without knowledge transfer. Our transferable optimization method makes transistor sizing and design porting more effective and efficient.

Conducted EMI issues in a 600-W single-phase boost PFC design

Abstract: This paper presents the results of experimental activity concerned with the development of a 600 W boost power-factor corrector (PFC) complying with the EMC standards for conducted EMI in the 150 kHz 30 MHz range. In order to accomplish this task, different circuit design and layout solutions are taken into account and their effect on the conducted EMI behavior of the converter is experimentally evaluated. Common-mode and differential-mode switching noise, together with input filters' design and topology and with the printed circuit board layout (in terms of track length and spacing, ground and shielding planes, etc.) are the key aspects which have been considered. In particular, the paper reports the conducted EMI measurements for different filter capacitor placements and values, for different power switch drive circuits, together with several other provisions which have turned out to be decisive in the reduction of the generated EMI.