Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

Topology conserving mappings for learning motor tasks

Abstract: Topology conserving mappings play an important role for biological processing of sensory input. We suggest that principles found capable of establishing such maps can also be applied to organize the learning of motor tasks. As an example we consider the task of learning to balance a pole.

Integrated backplane interconnection architecture

Abstract: A backplane, provides a physical layer level interconnection between a plurality of modules. The backplane includes a physical layer inplementation of an interconnection topology incorporated within one or more integrated circuits called interconnect chips. Incorporated on the interconnect chips are interconnect drivers and interconnect receivers for the physical layer implementation of the interconnection topology. These interconnect drivers and interconnect receivers provide point-to-point links between the physical layer implementation of the interconnection topology and the plurality of modules. Each point-to-point link may include two separate point-to-point link lines, one for an interconnect driver and one for an interconnect receiver. For the bus interconnection topology, alternately, each point-to-point link may be tri-level, including only a single point-to-point link line. The interconnection topology may be, for example, a bus topology, a ring topology or a circuit switched topology.

Fault-Tolerant Neutral-Point-Clamped Converter Solutions Based on Including a Fourth Resonant Leg

Abstract: This paper presents a new three-level topology based on the neutral-point (NP)-clamped converter. An additional leg is added to the basic topology. The main purpose of this leg is to provide the converter with fault-tolerant capabilities. In addition, during normal operation mode, the fourth leg can be used to balance the NP voltage. In this way, the low-frequency voltage oscillations that appear in the NP under some operating conditions are cancelled out effectively. As a result, the modulation strategy of the three main legs of the converter does not have to take care of the voltage balance and can focus on other aspects such as, for instance, minimizing the switching losses of the converter. However, the inclusion of the fourth leg produces some additional losses. A resonant topology is proposed to minimize the switching losses of this leg. Three different fault-tolerant solutions based on the fourth-leg topology are presented. A comparison of these topologies showing their respective advantages and drawbacks is made. Experimental results are presented to show the viability of this approach.

Multi-Input Switched-Capacitor Multilevel Inverter for High-Frequency AC Power Distribution

Abstract: This paper proposes a switched-capacitor multilevel inverter for high-frequency ac power distribution systems. The proposed topology produces a staircase waveform with higher number of output levels employing fewer components compared to several existing switched-capacitor multilevel inverters in the literature. This topology is beneficial where asymmetric dc voltage sources are available, e.g., in case of renewable energy farms based ac microgrids and modern electric vehicles. Utilizing the available dc sources as inputs for a single inverter solves the major problem of connecting several inverters in parallel. Additionally, the need to stack voltage sources, like batteries or supercapacitors, in series which demand charge equalization algorithms, are eliminated as the voltage sources employed share a common ground. The inverter inherently solves the problem of capacitor voltage balancing as each capacitor is charged to the value equal to one of the input voltage every cycle. State analysis, losses, and the selection of capacitance are examined. Simulation and experimental results at different distribution frequencies, power levels, and output harmonic content are provided to demonstrate the feasibility of the proposed multilevel inverter topology.

Automatic schematic diagram generation using topology information

Abstract: A netlist of a schematic diagram is generated. The netlist indicates the connectivity of components through connection lines. A normal display mode is provided in which at least a portion of the components are presented on the display, and connection lines corresponding to the components are also displayed. A topology display mode is provided in which the components are presented on the display without the connection lines. The user can switch between the topology display mode and the normal display mode while editing the schematic diagram. Automatic pin assignment and routing of the connection lines is performed according to the netlist, and is based upon grouping similarly classified connection lines. An abstract display mode is provided that presents abstract lines for a selected component, with a single abstract line running between two connected components. The abstract display mode is combinable with the topology display mode. Finally, the automatic positioning of components according to predefined topology templates is provided.