Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

Z-source-based multilevel inverter with reduction of switches

Abstract: This study presents a new inverter topology based on mixture of cascaded basic units and one H-bridge unit. The basic unit includes one Z source, one DC voltage source and two switches generating two voltage levels. The cascaded basic units produce positive and zero-voltage levels and in the same time suggested inverter obtains positive, zero- and negative voltage levels, as a result the number of power semiconductor switches is reduced with respect to traditional multilevel inverters. In this topology, output voltage amplitude is not limited to DC sources voltage summation similar to traditional cascaded multilevel inverters and can be boosted with Z network shoot-through state control; therefore other DC/DC converters are not needed and it is more reliable against short circuit. Besides as compared with traditional Z -source inverter, total harmonic distortion of injected voltage is decreased in the suggested inverter topology. The performance of proposed topology and its controller are validated with simulation results using MATLAB/SIMULINK software and the validity of the proposed multilevel inverter-based Z source is verified by experimental results.

Application-Aware Topology Reconfiguration for On-Chip Networks

Abstract: In this paper, we present a reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented. When a new application starts, the proposed NoC tailors its topology to the application traffic pattern by changing the inter-router connections to some predefined configuration corresponding to the application. It addresses one of the main drawbacks of the existing application-specific NoC optimization methods, i.e., optimization of NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC when several different applications are integrated into a single modern and complex multicore system-on-chip or chip multiprocessor. The proposed reconfigurable NoC architecture supports multiple applications by appropriately configuring itself to a topology that matches the traffic pattern of the currently running application. This paper first introduces the proposed reconfigurable topology and then addresses the problems of core to network mapping and topology exploration. Further on, we evaluate the impact of different architectural attributes on the performance of the proposed NoC. Evaluations consider network latency, power consumption, and area complexity.

Implantable defibrillator system with capacitor switching circuitry

Abstract: The present invention uses switches to set the topology and polarity of a circuit that includes capacitors to deliver an electric pulse to a heart during a defibrillation procedure. The waveform of the electric pulse is biphasic, in that it is a positive portion of the pulse followed by a negative portion of the pulse. The topology and polarity of the circuit are utilized to produce a waveform that approximates the ideal waveform for the specific situation. The circuit provides for combinations of capacitors variously in series and in parallel and changing the topology and polarity of the circuit during discharge of the capacitors.

The REFINE multiprocessor—theoretical properties and algorithms

Abstract: A reconfigurable interconnection network based on a multi-ring architecture called REFINE is described. REFINE embeds a single 1-factor of the Boolean hypercube in any given configuration. The mathematical properties of the REFINE topology and the hardware for the reconfiguration switch are described. The REFINE topology is scalable in the sense that the number of interprocessor communication links scales linearly with network size whereas the network diameter scales logarithmically with network size. Primitive parallel operations on the REFINE topology are described and analyzed. These primitive operations could be used as building blocks for more complex parallel algorithms. A large class of algorithms for the Boolean n-cube which includes the FFT and the Batcher's bitonic sort is shown to map efficiently on the REFINE topology. The REFINE multiprocessor is shown to offer a cost-effective alternative to the Boolean n-cube multiprocessor architecture without substantial loss in performance.