Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

Design of logical topologies for wavelength-routed optical networks

Abstract: The problem of designing a logical topology over a wavelength-routed all-optical network (AON) physical topology is studied. The physical topology consists of the nodes and fiber links in the network. On an AON physical topology, we can set up lightpaths between pairs of nodes, where a lightpath represents a direct optical connection without any intermediate electronics. The set of lightpaths along with the nodes constitutes the logical topology. For a given network physical topology and traffic pattern, our objective is to design the logical topology and the routing algorithm so as to minimize the network congestion while constraining the average delay seen by a source-destination pair and the amount of processing required at the nodes (degree of the logical topology). Ignoring the delay constraints can result in fairly convoluted logical topologies with very long delays. On the other hand, in all our examples, imposing it results in a minimal increase in congestion. While the number of wavelengths required to imbed the resulting logical topology on the physical all optical topology is also a constraint in general, we find that in many cases of interest this number can be quite small. We formulate the combined logical topology design and routing problem described above as a mixed integer linear programming problem which we then solve for a number of cases of a six-node network. This programming problem is split into two subproblems: logical topology design, and routing. We then compare the performance of several heuristic topology design algorithms against that of randomly generated topologies, as well as lower bounds.

The auxiliary resonant commutated pole converter

Abstract: The auxiliary resonant commutated pole (ARCP), a new power converter topology that fully achieves soft switching without increasing primary device voltage or current ratings, is discussed. The ARCP converter is capable of true pulse-width modulation (PWM) control of each phase. The power circuit relies on the addition of an auxiliary triggered resonant commutation circuit or snubber to commutate the inductive load current from a main diode to an active device, allowing a zero voltage turn-off of the main devices. The auxiliary devices operate in a zero current soft switching mode, thereby requiring minimal current turn-off capability. The operation and control of the ARCP converter are discussed. Its performance is analyzed, and a simulation is presented. It is shown that the ARCP converter is capable of operation at elevated switching frequencies (10-30 kHz), high power levels (200-1000 kW), and high conversion efficiencies. the auxiliary devices will typically account for a 20% increase in the total silicon area of a three-phase power converter. >

A Cascade Multilevel Converter Topology With Reduced Number of Switches

Abstract: This paper introduces a new multilevel converter topology that has many steps with fewer power electronic switches. The proposed circuit consists of series-connected submultilevel converters blocks. The optimal structures of this topology are investigated for various objectives, such as minimum number of switches and capacitors, and minimum standing voltage on switches for producing maximum output voltage steps. A new algorithm for determination of dc voltage sourcespsila magnitudes has also been presented. The proposed topology results in reduction of the number of switches, losses, installation area, and converter cost. The operation and performance of the proposed multilevel converter has been verified by the simulation and experimental results of a single-phase 53-level multilevel converter.

A Structure Preserving Model for Power System Stability Analysis

Abstract: A new model for the study of power system stability via Lyapunov functions is proposed. The key feature of the model is an assumption of frequency-dependent load power, rather than the usual impedance loads which are subsequently absorbed into a reduced network. The original network topology is explicitly represented. This approach has the important advantage of rigorously accounting for real power loads in the Lyapunov functions. This compares favorably with existing methods involving approximations to allow for the significant transfer conductances in reduced network models. The preservation of network topology can be exploited in stability analysis, with the concepts of critical and vulnerable cutsets playing central roles in dynamic and transient stability evaluation respectively. Of fundamental importance is the feature that the Lyapunov functions give a true representation of the spatial distribution of stored energy in the system

A Single-Stage Grid Connected Inverter Topology for Solar PV Systems With Maximum Power Point Tracking

Abstract: This paper proposes a high performance, single-stage inverter topology for grid connected PV systems. The proposed configuration can not only boost the usually low photovoltaic (PV) array voltage, but can also convert the solar dc power into high quality ac power for feeding into the grid, while tracking the maximum power from the PV array. Total harmonic distortion of the current, fed into the grid, is restricted as per the IEEE-519 standard. The proposed topology has several desirable features such as better utilization of the PV array, higher efficiency, low cost and compact size. Further, due to the very nature of the proposed topology, the PV array appears as a floating source to the grid, thereby enhancing the overall safety of the system. A survey of the existing topologies, suitable for single-stage, grid connected PV applications, is carried out and a detailed comparison with the proposed topology is presented. A complete steady-state analysis, including the design procedure and expressions for peak device stresses, is included. Necessary condition on the modulation index "M" for sinusoidal pulsewidth modulated control of the proposed inverter topology has also been derived for discontinuous conduction mode operation. All the analytical, simulation and experimental results are presented.