Topology (electrical circuits)

About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.

On the Energy Efficiency of Physical Topology Design for IP Over WDM Networks

Abstract: The energy consumption of information and communications technology networks is increasing rapidly as a result of the Internet expansion in reach and capacity. In this paper, we investigate energy-efficient physical topologies for backbone IP over wavelength-division multiplexing (WDM) networks. We develop a mixed integer linear programming model to optimize the physical topology of IP over WDM networks with the objective of minimizing the network total power consumption. We consider the National Science Foundation network topology and compare its energy consumption with the energy consumption of optimized physical topologies under different IP over WDM approaches and nodal degree constraints. We study the physical topology optimization under a symmetric full-mesh connectivity traffic matrix and an asymmetric traffic demand, where data centers create a hot node scenario in the network. We also investigate the power savings obtained by deploying topologies that eliminate the need for IP routers, including a full-mesh topology and a star topology. Simulation results show that the full-mesh and star topologies result in significant power savings of 95% and 92%, respectively. Furthermore, the optimization of the physical topology is investigated considering the presence of renewable energy sources in the network. The results show that optimizing the physical topology increases the utilization of the renewable energy sources.

A Distributed TDMA Slot Assignment Algorithm for Wireless Sensor Networks

Abstract: Wireless sensor networks benefit from communication protocols that reduce power requirements by avoiding frame collision. Time Division Media Access methods schedule transmission in slots to avoid collision, however these methods often lack scalability when implemented in \emph{ad hoc} networks subject to node failures and dynamic topology. This paper reports a distributed algorithm for TDMA slot assignment that is self-stabilizing to transient faults and dynamic topology change. The expected local convergence time is O(1) for any size network satisfying a constant bound on the size of a node neighborhood.

Selective Harmonic Mitigation Technique for Cascaded H-Bridge Converters With Nonequal DC Link Voltages

Abstract: Multilevel converters have received increased interest recently as a result of their ability to generate high quality output waveforms with a low switching frequency. This makes them very attractive for high-power applications. A cascaded H-bridge converter (CHB) is a multilevel topology which is formed from the series connection of H-bridge cells. Optimized pulse width modulation techniques such as selective harmonic elimination or selective harmonic mitigation (SHM-PWM) are capable of preprogramming the harmonic profile of the output waveform over a range of modulation indices. Such modulation methods may, however, not perform optimally if the dc links of the CHB are not balanced. This paper presents a new SHM-PWM control strategy which is capable of meeting grid codes even under nonequal dc link voltages. The method is based on the interpolation of different sets of angles obtained for specific situations of imbalance. Both simulation and experimental results are presented to validate the proposed control method.

Single-Stage Switched-Capacitor Module (S 3 CM) Topology for Cascaded Multilevel Inverter

Abstract: A two-stage switched-capacitor based multilevel inverter possesses a drawback such that switches in the second stage (i.e., H-bridge) endure higher voltage stress. To resolve this problem, this letter proposes a single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter, which ensures the peak inverse voltage across all the switches within the dc source voltage. A total of nine voltage levels can be generated with only one dc source and two incorporated capacitors. Hence, the number of isolated dc sources is significantly reduced compared to a cascaded H-bridge. In addition, voltage boosting gain of two is achieved. A comparative analysis of the recent topology reveals that the proposed S3CM topology achieves switch count reduction. The operation of the proposed topology is validated through circuit analysis followed by simulation and experimental results of a single-module (9-level) prototype.

Matrix converter topologies with reduced number of switches

Abstract: A direct AC-to-AC converter commonly termed a matrix converter has a simple structure and many attractive features. However, the complexity of its conventional PWM strategy is prone to commutation failure, which is a factor that keeps it from being utilized in industry. This paper focuses on several alternative dual-bridge matrix topologies which do not possess this problem. First, these converters have the same characteristics as a conventional matrix converter, such as four-quadrant operation, unity input power factor, no DC-link capacitor, and high quality voltage/current waveforms. Second, the number of switches can be reduced thus reducing the cost. Third, the switches on the line side can turn on and off at zero current, they do not have any difficult commutation problems. Lastly, the complexity of the clamp circuit in these topologies can be greatly simplified thereby further reducing the cost. This paper introduces several topologies with a reduced number of switches and analyzes the characteristics of this converter family. Simulation and experimental results of a 9-switch topology are provided to verify its feasibility.