Topic
Topology (electrical circuits)
About: Topology (electrical circuits) is a research topic. Over the lifetime, 33316 publications have been published within this topic receiving 397651 citations. The topic is also known as: topology.
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TL;DR: A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented, which implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications.
Abstract: A new approach for modulation of an 11-level cascade multilevel inverter using selective harmonic elimination is presented in this paper. The dc sources feeding the multilevel inverter are considered to be varying in time, and the switching angles are adapted to the dc source variation. This method uses genetic algorithms to obtain switching angles offline for different dc source values. Then, artificial neural networks are used to determine the switching angles that correspond to the real-time values of the dc sources for each phase. This implies that each one of the dc sources of this topology can have different values at any time, but the output fundamental voltage will stay constant and the harmonic content will still meet the specifications. The modulating switching angles are updated at each cycle of the output fundamental voltage. This paper gives details on the method in addition to simulation and experimental results.
146 citations
TL;DR: In this paper, an efficient mode-tracking method based on the modal assurance criterion (MAC) is formulated for the structural topology optimization of maximizing the eigenfrequencies of desired modes.
146 citations
07 Apr 2008
TL;DR: The architecture thus enables a generalized System.-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks.
Abstract: This paper presents a network-on-chip (NoC) architecture that enables the network topology to be reconfigured. The architecture thus enables a generalized System.-on-Chip (SoC) platform in which the topology can be customized for the application that is currently running on the chip, including long links and direct links between IP-blocks. The configurability is inserted as a layer between routers and links, and the architecture can therefore be used in combination with existing NoC routers, making it a general architecture. The topology is configured using energy-efficient topology switches based on physical circuit-switching as found in FPGAs. The paper presents the ReNoC (Reconfigurable NoC) architecture and evaluates its potential. The evaluation design shows a 56% decrease in power consumption compared to a static 2D mesh topology.
146 citations
TL;DR: Novel circuits for high-voltage digital level shifting with zero static power consumption and 50% less silicon area are presented, and exhibit a factor of 20-80 lower dynamic power consumption typically.
Abstract: We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.
146 citations
15 Jul 2002
TL;DR: This work proposes a graph topology which allows for very efficient broadcast and search, and describes a broadcast algorithm that exploits the topology to reach all nodes in the network with the minimum number of messages possible.
Abstract: Peer-to-peer networks are envisioned to be deployed for a wide range of applications However, P2P networks evolving in an unorganized manner suffer from serious scalability problems, limiting the number of nodes in the network, creating network overload and pushing search times to unacceptable limits We address these problems by imposing a deterministic shape on P2P networks: We propose a graph topology which allows for very efficient broadcast and search, and we describe a broadcast algorithm that exploits the topology to reach all nodes in the network with the minimum number of messages possible We provide an efficient topology construction and maintenance algorithm which, crucial to symmetric peer-to-peer networks, does neither require a central server nor super nodes in the network Nodes can join and leave the self-organizing network at any time, and the network is resilient against failure Moreover, we show how our scheme can be made even more efficient by using a global ontology to determine the organization of peers in the graph topology, allowing for efficient concept-based search
145 citations