scispace - formally typeset
Search or ask a question

Showing papers on "Total harmonic distortion published in 1997"


Journal ArticleDOI
TL;DR: In this paper, four control topologies for single-phase uninterruptible power system (UPS) inverters are presented and compared, with the common objective of providing a dynamically stiff, low total harmonic distortion (THD), sinusoidal output voltage.
Abstract: Four control topologies for single-phase uninterruptible power system (UPS) inverters are presented and compared, with the common objective of providing a dynamically stiff, low total harmonic distortion (THD), sinusoidal output voltage. Full-state feedback, full-state command controllers are shown, utilizing both filter inductor current and filter capacitor current feedback to augment output voltage control. All controllers presented include output voltage decoupling in a manner analogous to "back EMF" decoupling in DC motor drives. Disturbance input decoupling of the load current and its derivative is presented. An observer-based controller is additionally considered and is shown to be a technically viable, economically attractive option. The accuracy transfer function of the observer estimate is used to evaluate its measurement performance. Comparative disturbance rejection is evaluated by overlaying the dynamic stiffness (inverse of output impedance) frequency response of each controller on a single plot. Experimental results for one controller are presented.

403 citations


Proceedings ArticleDOI
05 Oct 1997
TL;DR: In this article, a power line conditioner (PLC) using a cascade multilevel inverter is presented for voltage regulation, reactive power (VAr) compensation and harmonic filtering.
Abstract: A power line conditioner (PLC) using a cascade multilevel inverter is presented for voltage regulation, reactive power (VAr) compensation and harmonic filtering in this paper. The cascade M-level inverter consists of (M-1)/2 H-bridges in which each bridge has its own separate DC source. This new inverter: (1) can generate almost an sinusoidal waveform voltage with only one time switching per line cycle; (2) can eliminate transformers of multipulse inverters used in the conventional static VAr compensators; and (3) makes possible direct connection to the 13.8 kV power distribution system in parallel and series without any transformer. In other words, the power line conditioner is much more efficient and more suitable to VAr compensation and harmonic filtering of distribution systems than traditional multipulse and pulse width modulation (PWM) inverters. It has been shown that the new inverter is specially suited for VAr compensation. This paper focuses on feasibility and control schemes of the cascade inverter for voltage regulation and harmonic filtering in distribution systems. Analytical, simulated and experimental results show the superiority of the new power line conditioner.

368 citations


Journal ArticleDOI
TL;DR: In this article, a shunt active filter based on detection of voltage at the point of installation is compared to others, and the best site selection is not the beginning terminal but the end terminal of the primary line in the feeder.
Abstract: This paper deals with a shunt active filter which will be installed by an electric utility, putting much emphasis on the control strategy and the best point of installation of the shunt active filter on a feeder in a power distribution system. The objective of the shunt active filter is to damp harmonic propagation, which results from harmonic resonance between many capacitors for power factor improvement and line inductors in the feeder, rather than to minimize voltage distortion throughout the feeder. Harmonic mitigation is a welcome "by-product" of the shunt active filter, which comes from damping of harmonic propagation. This paper concludes that the shunt active filter based on detection of voltage at the point of installation is superior in stability to others, and that the best site selection is not the beginning terminal but the end terminal of the primary line in the feeder. Computer simulation is performed to verify the validity and effectiveness of the shunt active filter by means of an analog circuit simulator, which is characterized by installing it on a feeder of a radial distribution system in a residential area.

353 citations


Journal ArticleDOI
TL;DR: In this article, a two-layer controller consisting of a tracking controller and a repetitive controller is proposed to improve both the transient and steady-state responses of a closed-loop regulated pulsewidth-modulated (PWM) inverter for high-quality sinusoidal AC voltage regulation.
Abstract: This paper proposes a new control scheme based on a two-layer control structure to improve both the transient and steady-state responses of a closed-loop regulated pulse-width-modulated (PWM) inverter for high-quality sinusoidal AC voltage regulation. The proposed two-layer controller consists of a tracking controller and a repetitive controller. Pole assignment with state feedback has been employed in designing the tracking controller for transient response improvement, and a repetitive control scheme was developed in synthesizing the repetitive controller for steady-state response improvement. A design procedure is given for synthesizing the repetitive controller for PWM inverters to minimize periodic errors induced by rectifier-type nonlinear loads. The proposed control scheme has been realized using a single-chip digital signal processor (DSP) TMS320C14 from Texas Instruments. A 2-kVA PWM inverter has been constructed to verify the proposed control scheme. Total harmonic distortion (THD) below 1.4% for a 60-Hz output voltage under a bridge-rectifier RC load with a current crest factor of 3 has been obtained. Simulation and experimental results show that the DSP-based fully digital-controlled PWM inverter can achieve both good dynamic response and low harmonics distortion.

279 citations


Journal ArticleDOI
22 Jun 1997
TL;DR: In this article, a novel overmodulation technique for space-vector pulsewidth modulation (PWM) inverters is proposed, which produces a linear relationship between the output voltage and the modulation index up to six-step operation.
Abstract: In this paper, a novel overmodulation technique for space-vector pulsewidth modulation (PWM) inverters is proposed. The overmodulation range is divided into two modes depending on the modulation index (MI). In mode I, the reference angles are derived from the Fourier series expansion of the reference voltage which corresponds to the MI. In mode II, the holding angles are also derived in the same way. The strategy, which is easier to understand graphically, produces a linear relationship between the output voltage and the MI up to six-step operation. The relationship between those angles and the MI can be written in lookup tables or, for real-time implementation, can be piecewise linearized. In addition, harmonic components and total harmonic distortion (THD) of the output voltage are analyzed. When the method is applied to the V/f control of an induction motor, a smooth operation during transition from the linear control range to the six-step mode is demonstrated through experimental results.

231 citations


Journal ArticleDOI
TL;DR: A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented, using an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency.
Abstract: A low-noise multibit sigma-delta analog-to-digital converter (ADC) architecture suitable for operation at low oversampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6-/spl mu/m CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 V/3 V analog/digital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion (THD) of -98 dB with a 100-kHz input signal.

207 citations


Journal ArticleDOI
TL;DR: In this article, the authors present a basic control system which enables the UPFC to follow the changes in reference values of the active and reactive power supplied from the outer system controller, based on the transformation of the three-phase power system to the rotating reference frame.
Abstract: A unified power flow controller (UPFC) is a typical FACTS device capable of instantaneous control of three power system parameters. This paper presents a basic control system which enables the UPFC to follow the changes in reference values of the active and reactive power supplied from the outer system controller. The analysis is based on the transformation of the three-phase power system to the rotating reference frame. As a step closer to a practical application of the UPFC, a modified control structure with a predictive control loop and precontrol signal for a DC-voltage control was designed. The new control system offers better stability and transient performance in comparison with the classical decoupled strategy, especially considering the harmonic distortion of the current being controlled. The derived basic control of the UPFC was tested with the NETOMAC program system.

203 citations



Journal ArticleDOI
TL;DR: A novel randomized control strategy for three-phase voltage source inverters, based on voltage space vectors, is described, which results in switching losses in the inverter being reduced by about half in comparison with those using the classic space vector pulsewidth PWM method.
Abstract: A novel randomized control strategy for three-phase voltage source inverters, based on voltage space vectors, is described. An implicit asymmetrical modulating function results in switching losses in the inverter being reduced by about half in comparison with those using the classic space vector pulsewidth PWM method. The pulse rate is varied within individual 60/spl deg/ sectors of the vector plane, so that the power spectra of the output voltage are spread over a wide frequency range and acquire a continuous part. Relevant theoretical analyses, computer simulations and experimental results are presented.

180 citations


Proceedings ArticleDOI
03 Nov 1997
TL;DR: An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise and is particularly suitable for sigma-delta converters.
Abstract: An accurate and simple method is introduced for determining the third order polynomial that best fits a set of data points containing random noise. The coefficients of the polynomial are translated into offset, gain, and harmonic distortion for an analog-to-digital converter (ADC) driven by a digital-to-analog converter (DAC) or other appropriate signal source. The algorithm is efficient enough to be implemented as a built-in self-test for an IC, and is particularly suitable for sigma-delta converters.

162 citations


Proceedings ArticleDOI
07 Jul 1997
TL;DR: A multilevel pulse-width modulated (PWM) single phase voltage-source inverter topology for photovoltaic applications with use of the phase opposition (PO) carrier disposition multicarrier PWM switching technique is presented.
Abstract: A multilevel pulse-width modulated (PWM) single phase voltage-source inverter topology for photovoltaic applications is discussed in this paper. The use of the phase opposition (PO) carrier disposition multicarrier PWM switching technique for this topology is presented. Inverter switch control signals are derived. A 5-level and a 3-level PWM voltage waveform across the load is generated, for high and low modulation indexes respectively. Performance characteristics including total harmonic distortion for a range of operating conditions of the inverter are provided. Theoretical considerations discussed in this paper are supported with simulation and experimental results taken from a low power laboratory prototype.

Journal ArticleDOI
TL;DR: It is shown that the switching frequency reduction is achieved with no penalty in the line current harmonic distortion and a significant reduction of AC line current distortion is obtained with the modified dead-band technique for modulation indexes greater than 0.4.
Abstract: On-line pulsewidth modulation (PWM) pattern generators for current-source rectifiers and inverters offer a number of control advantages over off-line optimized patterns. However, when implemented using the principles which apply to voltage-source inverter PWM pattern generators, the switching frequency is equal to: (1) the carrier frequency in standard carrier-based implementations and (2) a function of the cycle frequency, sequence of space vectors, and selection of the zero space vector in space vector implementations. This paper shows that this frequency can be reduced to one-half of the respective frequencies. Two pattern generators are investigated: (1) an analog on-line carrier-based technique, namely, the modified dead-band technique and (2) a digital on-line space vector-based technique, where advantage is taken of the extra zero state available in current-source converters. It is shown that the switching frequency reduction is achieved with no penalty in the line current harmonic distortion. Moreover, a significant reduction of AC line current distortion is obtained with the modified dead-band technique for modulation indexes greater than 0.4. The principles of operation of the proposed schemes are explained, Experimental results on a 5 kVA current-source rectifier and a 5 kVA current-source inverter confirm the feasibility and features of the proposed pattern generators.

Proceedings ArticleDOI
22 Jun 1997
TL;DR: In this article, the authors presented the control circuit of a shunt active power filter based on the instantaneous active and reactive current i/sub d/-i/sub q/ method.
Abstract: This paper presents the control circuit of a shunt active power filter based on the instantaneous active and reactive current i/sub d/-i/sub q/ method The presented method is compared with the instantaneous active and reactive power p-q method under several mains voltage conditions and for different harmonic injection highpass filters The i/sub d/-i/sub q/ method as an excellent harmonic compensation performance and presents the advantage of being frequency-independent The DC voltage regulation system is analysed and its synthesis is performed Extensive simulation results are used to show the stability of the voltage regulation system and to establish the superior performance of i/sub d/-i/sub q/ method based compensator

Journal ArticleDOI
TL;DR: In this paper, the authors proposed two control issues: (1) regulation of the DC capacitance voltages and (2) their equalization to ensure the even sharing of voltage stresses in the gate-turn-off thyristors (GTOs), and (3) to prevent the degradation of total harmonic distortion (THD) factors, as all harmonic elimination strategies depend on equal voltages in their assumptions.
Abstract: Because of the high MVA ratings, it would be expensive to provide independent, equal, regulated DC voltage sources to power the multilevel converters which are proposed for STATCOMs. DC voltage sources can be derived from the DC link capacitances which are charged by the rectified AC power. This paper addresses two control issues: (1) regulation of the DC capacitance voltages and (2) their equalization. Equalization is necessary (i) to ensure the even sharing of voltage stresses in the gate-turn-off thyristors (GTOs), and (ii) to prevent the degradation of total harmonic distortion (THD) factors, as all harmonic elimination strategies depend on equal voltages in their assumptions. The strategies considered are: (a) the fundamental frequency method, and (b) the sinusoidal pulse width modulation method. Digital simulations are used to confirm the feasibility of the control methods.

Journal ArticleDOI
TL;DR: In this article, an alternative harmonic model for representing power system nonlinear loads by a "crossed-frequency" admittance matrix is presented, which is applicable to passive and stationary electrical loads assuming a constant fundamental frequency voltage.
Abstract: An alternative harmonic model for representing power system nonlinear loads by a "crossed-frequency" admittance matrix is presented in the paper. This harmonic model is applicable to passive and stationary electrical loads assuming a constant fundamental frequency voltage. Results of the proposed harmonic model are reported and compared with experimental tests.

Journal ArticleDOI
TL;DR: In this article, the authors present a method for predicting the net harmonic currents produced by a large number of electric vehicle (EV) battery chargers, which is stochastically formulated in order to account for randomness in individual charger start-time and battery state-of-charge.
Abstract: This paper presents a method for predicting the net harmonic currents produced by a large number of electric vehicle (EV) battery chargers. The problem is stochastically formulated in order to account for randomness in individual charger start-time and battery state-of-charge. The authors introduce a model that allows for partial harmonics cancellation due to diversity in magnitudes and phase angles. A general solution technique is presented along with an example using data from a commercially available EV charger. Their results show that a limiting distribution of 7-10 chargers is adequate for accurately predicting harmonic injection currents using the central limit theorem. They also show that the expected values of net harmonic currents are considerably less than the peak values that would have been realized if the same number of chargers were operated in unison.

Journal ArticleDOI
TL;DR: This paper deals with a new multilevel high-voltage source inverter with gate-turn-off (GTO) thyristors, which deals with safe high-power conversion systems independent of the dynamic switching characteristics of each power semiconductor device.
Abstract: This paper deals with a new multilevel high-voltage source inverter with gate-turn-off (GTO) thyristors. Recently, a multilevel approach seemed to be the best suited for implementing high-voltage power conversion systems because it leads to a harmonic reduction and deals with safe high-power conversion systems independent of the dynamic switching characteristics of each power semiconductor device. A conventional multilevel inverter has some problems; voltage unbalance between DC-link capacitors and larger blocking voltage across the inner switching devices. To solve these problems, the novel multilevel inverter structure is proposed.

Journal ArticleDOI
I. Mehr1, D.R. Welland
TL;DR: In this article, a programmable seven-pole two-asymmetric zero filter implementation is described based on a new transconductance (G/sub m/) cell, and the impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed.
Abstract: Design techniques for equiripple phase CMOS continuous-time filters are presented, and their integration within a partial-response maximum likelihood (PRML) disk drive read channel is discussed. A programmable seven-pole two asymmetric zero filter implementation is described based on a new transconductance (G/sub m/) cell. The impact of integrator finite output impedance, excess phase, and other implementation related nonidealities is discussed. A filter tuning circuit that requires an accurate time base but no external components is presented. The filter has a cutoff frequency (f/sub c/) range of 6-43 MHz, where f/sub c/ is the -3 dB point of the magnitude transfer function with the two zeros set to infinity. Also, with finite zeros it is able to provide up to 12 dB of boost which is defined as the maximum value of the magnitude transfer function referred to dc. The group delay ripple stays within /spl plusmn/2% for frequencies below 1.75 f/sub c/. The cutoff frequency exhibits a 650 ppm//spl deg/C temperature dependency and a variation of /spl plusmn/1%/V with the power supply. Total harmonic distortion (THD) values are below -40 dB at twice the nominal operating input voltage (V/sub nominal/=320 mV peak-to-peak differential), and the dynamic range exceeds 60 dB (for a maximum input signal of 640 mV peak-to-peak differential, maximum bandwidth setting, and no boost). Both the filter and a tuning circuit were implemented in a 0.6-/spl mu/m single-poly triple-metal n-well CMOS process. They consume 90 mW from a single 5 V power supply and occupy an area of 0.8 mm/sup 2/.

Journal ArticleDOI
TL;DR: In this paper, a frequency domain arc furnace model for iterative harmonic analysis by means of a Newton method is presented, which offers a three-phase configuration where there is no path for homopolar currents.
Abstract: This paper presents a new frequency domain arc furnace model for iterative harmonic analysis by means of a Newton method. Powerful analytical expressions for harmonic currents and their derivatives are obtained under balanced conditions of the power system. The model offers a three-phase configuration where there is no path for homopolar currents. Moreover, it contemplates continuous and discontinuous evolution of the arc current. The solution obtained is validated by means of time domain simulations. Finally, the model was integrated in a harmonic power flow where studies have been performed in a network with more than 700 busbars and 7 actual arc furnace loads.

Journal ArticleDOI
TL;DR: In this paper, a linear, fully balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with large dc gain and wide bandwidth is described, which uses a two-differential-pair transconductor with a cross-coupled input stage together with a negative resistance load for compensating the parasitic output resistance of the OTA.
Abstract: A linear, fully balanced, voltage-tunable CMOS operational transconductance amplifier (OTA) with large dc gain and wide bandwidth is described. The approach uses a two-differential-pair transconductor with a cross-coupled input stage together with a negative resistance load for compensating the parasitic output resistance of the OTA. Since no additional internal nodes are generated, dc gain enhancement is obtained without bandwidth limitation. SPICE simulations show that total harmonic distortion at 1.42 V/sub p-p/ is less than 1% with dynamic range equal to 66 dB at a power consumption of 2.7 mW from a single 5-V supply. As an example, the OTA is used to design a third-order elliptic lowpass filter in the very-high-frequency range, simulated in a standard 2 /spl mu/m CMOS process (MOSIS). The cutoff frequency of the filter is tunable in the range of 12-50 MHz.

Proceedings ArticleDOI
05 Oct 1997
TL;DR: A converter structure, based on a multilevel cascade of single phase converters, which can be coupled to the transmission system without transformers is proposed, which includes low injected voltage harmonic distortion and fast response to changes in the compensation level.
Abstract: Series VAr compensators based on force commutated static power converters are proving to be a viable alternative to shunt compensators as a means of enhancing power transmission and distribution capability. This paper proposes a converter structure, based on a multilevel cascade of single phase converters, which can be coupled to the transmission system without transformers. The individual converters are switching at very low frequencies, resulting in high efficiency, and are fed from independent self controlled DC capacitor buses. Advantages of the proposed series compensator include low injected voltage harmonic distortion and fast response to changes in the compensation level. Pattern generation options are presented. Gating and control schemes are discussed. Simulation results are verified experimentally.

Journal ArticleDOI
01 Jan 1997
TL;DR: In this article, the authors describe a unit based on an 8-bit microprocessor which enables continuous real-time tracking of the harmonics in the voltage or current waveforms of a power system.
Abstract: The paper describes a unit based on an 8-bit microprocessor which enables continuous real-time tracking of the harmonics in the voltage or current waveforms of a power system. The unit is part of a distributed system for monitoring and controlling a power system which applies a 12-state Kalman filter to the voltage or current samples to obtain in real time the instantaneous values for a maximum of six harmonics as well as the existing harmonic distortion. The unit maintains a buffer in memory with the magnitudes of the harmonics detected in the last second and generates an alarm signal when the distortion level of an individual harmonic, or that of the group as a whole, exceeds the threshold established by the international standard.

Journal ArticleDOI
TL;DR: In this article, a time quantity one-cycle control method is proposed for unity power-factor AC-DC power converters, which operate at constant switching frequency, require no current sensing, and exhibit resistive input impedance at the AC side.
Abstract: A time quantity one-cycle control method is proposed in this paper for unity power-factor AC-DC power converters. Power converters controlled by this method operate at constant switching frequency, require no current sensing, have a simple control circuit and exhibit resistive input impedance at the AC side. A feedback loop design method is provided to minimize the current distortion when the output voltage ripple is not negligible. Experimental results confirmed the theoretical prediction.

Journal ArticleDOI
TL;DR: The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication and the operational transconductance amplifier used in this filter are presented.
Abstract: The design and performance of a rail-to-rail low-voltage CMOS fifth-order elliptic low-pass GM-C filter for baseband mobile communication are presented. The operational transconductance amplifier (OTA) used in this filter is a low-voltage rail-to-rail voltage-to-current converter (V-I converter). In this V-I converter, an N-type V-I converter cell is connected in parallel with its counterpart, a P-type V-I converter cell, to achieve common-mode (CM) rail-to-rail operation. Two maximum-current selecting circuits and an output current subtraction circuit are utilized to generate constant-g/sub m/ output currents for this OTA. This fifth-order elliptic low-pass GM-C filter operates at a supply voltage of 3 V and has a cutoff frequency of 280 to 405 kHz. It provides up to 700 mV/sub pp/ output with 1% total harmonic distortion (THD), dissipates 2.48 mW at V/sub cm/=1.5 V, and occupies 1.62 mm/sup 2/ in a 1.2-/spl mu/m CMOS technology.

Proceedings ArticleDOI
23 Feb 1997
TL;DR: In this article, three space vector modulation schemes are analyzed for a four-leg voltage source inverter with respect to switching losses and total harmonic distortion under both balanced and unbalanced load conditions over the entire range of modulation index values and over varying load power factor angle.
Abstract: Three space vector modulation schemes are analyzed for a four-leg voltage source inverter. The analysis is performed with respect to switching losses and total harmonic distortion under both balanced and unbalanced load conditions over the entire range of modulation index values and over varying load power factor angle. The analysis has been verified using simulation.

Journal ArticleDOI
TL;DR: In this paper, the relationship between the relative frequency of a harmonic and its sequence (positive/negative) was derived for both voltage-source and current-source power converters.
Abstract: Harmonic transfer from DC-side to AC-side and vice-versa through a three-phase bridge power converter is treated by using space vectors. The dependency of the relative frequency of a harmonic and its sequence (positive/negative) is illustrated. It is shown that the derived relationships are valid for both voltage-source and current-source power converters. Thereby, the relationships for the frequency transformation through power converters are also valid for both voltage and current harmonics. This analytical method is validated by digital simulations with EMTP software.

Proceedings Article
A.F. Duisters1, E.C. Dijkmans
01 Jan 1997
TL;DR: In this paper, a CMOS rail-to-rail input operational amplifier with THD performance of -90 dB has been presented and the operation of the opamp is based on a standard two-stage Miller configuration and is capable of driving a low ohmic load.
Abstract: This paper describes the principle and design of a CMOS Rail-to-Rail input operational amplifier with THD performance of -90 dB. The operation of the opamp is based on a standard two-stage Miller configuration and is capable of driving a low ohmic load (32 Ω). THD levels below -90 dB has not yet been shown with existing Rail-to-Rail techniques. The Rail-to-Rail functionality is achieved with a new area efficient on chip charge pump circuit for the generation of the supply voltage for the input differential pair.

Proceedings ArticleDOI
11 May 1997
TL;DR: In this article, the authors present an approach for limiting harmonic and improving reactive compensation for industrial power systems using single-tuned filters using a power distribution model that incorporates both the filter's capacity and resonant point as design parameters.
Abstract: The objective of this paper is to present a novel approach for limiting harmonic and improving reactive compensation for industrial power systems using single-tuned filters. The unique feature of the developed power distribution model is that it incorporates both the filter's capacity and resonant point as design parameters. The model also considers the de-tuning effects due to temperature and frequency variations, as well as manufacturing tolerances. The proposed approach was implemented as a PC-based computer code, and it was integrated with a user-friendly graphical user interface. The developed analysis tool was employed to solve the harmonic problems of several industrial plants, and the results all showed great improvements after using this computer tool.

Journal ArticleDOI
TL;DR: In this article, the design of very small ac transconductance voltage to current transducers for low frequency continuous-time filters, very large resistors and other applications is discussed.
Abstract: This paper deals with the design of very small ac transconductance voltage to current transducers intended for the design of low frequency continuous-time filters, very large resistors and other applications. The first type of Operational Transconductance Amplifiers (OTA) is based on a triode biased transistor and a current division technique. The second one uses partial positive feedback which allows to reduce transistor dimensions but the sensitivity to transistor mismatches increases. The proposed techniques can be used for the design of high-order low frequency IC filters, ladder or based on biquads, with moderated transistor dimensions while the dynamic range-cutoff frequency performance is comparable to previously reported structures. A 10 Hz third order lowpass ladder filter has been designed with these techniques, and it shows a dynamic range of 62 dB. Besides, a novel biasing technique for capacitive sources coupled preamplifiers is proposed. Experimental results for a prototype, fabricated in a 1.2 μm CMOS process, have shown very low distortion components (THD< 1 level below 15 μ V_RMS and dynamic range of 63 dB. The power consumption is only 10 μwatts and the supply voltages are ± 1.5 volts.

Journal ArticleDOI
TL;DR: In this paper, a third-order class AB current-mode Chebyshev filter based on the log-domain instantaneous companding principle and integrated in a 1/spl mu/m BiCMOS process is presented.
Abstract: A third-order class AB current-mode Chebyshev filter based on the log-domain instantaneous companding principle and integrated in a 1-/spl mu/m BiCMOS process is presented. It has a nominal cutoff frequency of 320 kHz corresponding to a bias current of 1 /spl mu/A and can be frequency tuned over almost three decades up to about 10 MHz. It operates with a nominal supply voltage of 1.2 V maintaining a dynamic range at 1% total harmonic distortion (THD) of 65 dB. For cutoff frequencies in the range of 10 kHz, the supply voltage can be reduced down to 0.9 V. Typical to companding systems, the class AB filter shows a measured SNR versus input signal that saturates to a maximum value which for this particular realization is 52.5 dB. It has an active area of 0.55 mm/sup 2/ and dissipates 65 /spl mu/W, leading to a power consumption per pole and edge frequency of 67.7 pJ. These results demonstrate the potential of instantaneous companding filters for very low-voltage and low-power applications with moderate linearity and SNR requirements.