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Showing papers on "Transactional memory published in 1990"


Proceedings ArticleDOI
26 Jun 1990
TL;DR: This work focuses on a protocol which ensures the atomic update of blocks into stable transactional memory when they have been modified by several caches.
Abstract: Some aspects of a fault-tolerant tightly coupled multiprocessor architecture are presented. The originality of this architecture resides in the use of a stable transactional memory shared by all processors. To ensure fault tolerance, each update of a memory block is included into an atomic transaction managed by the stable transactional memory. All the blocks that are part of a transaction are written back atomically into stable transaction memory. This work focuses on a protocol which ensures the atomic update of blocks into stable transactional memory when they have been modified by several caches. The results of various simulations that were conducted in order to evaluate the potential performance of the proposed architecture are also presented. >

33 citations


01 Jan 1990
TL;DR: The architecture presented in this report solves the problem of tightly coupled multiprocessors by encapsulating the memory modifications done by a process into an atomic transaction and presenting potential performance for this architecture the data for which was obtained through simulation.
Abstract: Traditionally, tightly coupled multiprocessors allow data sharing between multiple caches by keeping cached copies of memory blocks coherent with respect to shared memory. This is difficult to achieve in a fault tolerant environment due to the need to save global checkpoints in shared memory from where consistent cache states can be recovered after a failure. The architecture presented in this report solves this problem by encapsulating the memory modifications done by a process into an atomic transaction. Caches record dependencies between the transactions associated with processes modifying the same memory blocks. Dependent transactions may then be atomically committed. Such an operation requires a cache coherence protocol responsible for recording process dependencies as well as keeping coherent cached copies of blocks and a shared stable transactional memory owing to which all memory updates are atomic to allow recovery after a processor failure. This report also presents potential performance for this architecture the data for which was obtained through simulation.

1 citations