Showing papers on "Transactional memory published in 1997"

Software transactional memory

Abstract: As we learn from the literature, flexibility in choosing synchronization operations greatly simplifies the task of designing highly concurrent programs. Unfortunately, existing hardware is inflexible and is at best on the level of a Load–Linked/Store–Conditional operation on a single word. Building on the hardware based transactional synchronization methodology of Herlihy and Moss, we offer software transactional memory (STM), a novel software method for supporting flexible transactional programming of synchronization operations. STM is non-blocking, and can be implemented on existing machines using only a Load–Linked/Store–Conditional operation. We use STM to provide a general highly concurrent method for translating sequential object implementations to non-blocking ones based on implementing a k-word compare&swap STM-transaction. Empirical evidence collected on simulated multiprocessor architectures shows that our method always outperforms the non-blocking translation methods in the style of Barnes, and outperforms Herlihy’s translation method for sufficiently large numbers of processors. The key to the efficiency of our software-transactional approach is that unlike Barnes style methods, it is not based on a costly “recursive helping” policy.

Transparent Support for Wait-Free Transactions

Abstract: This paper concerns software support for non-blocking transactions in shared-memory multiprocessors. We present mechanisms that convert sequential transactions into lock-free or wait-free ones. In contrast to some previous mechanisms, ours support transactions for which the set of memory locations accessed cannot be determined in advance. Our implementations automatically detect and resolve conflicts between concurrent transactions, and allow transactions that do not conflict to execute in parallel. The key to the efficiency of our wait-free implementation lies in using a lock-free (but not wait-free) multi-word compare-and-swap (MWCAS) operation. By introducing communication between a high-level helping mechanism and the lock-free MWCAS, we show that an expensive wait-free MWCAS is not necessary to ensure wait-freedom.

Architectural Transactional Memory: Support for Lock-Free Data Structures

Abstract: A shared data structure is lock-free if its operations do not require mutual exclusion. If one process is interrupted in the middle of an operation, other processes will not be prevented from operating on that object. In highly concurrent systems, lock-free data structures avoid common problems associated with conventional locking techniques, including priority inversion, convoying, and difficulty of avoiding deadlock. This paper introduces transactional memory, a new multiprocessor architecture intended to make lock-free synchronization as efficient (and easy to use) as conventional techniques based on mutual exclusion. Transactional memory allows programmers to define customized read-modify-write operations that apply to multiple, independently-chosen words of memory. It is implemented by straightforward extensions to any multiprocessor cache-coherence protocol. Simulation results show that transactional memory matches or outperforms the best known locking techniques for simple benchmarks, even in the absence of priority inversion, convoying, and deadlock.

Scalable multicomputer object spaces: a foundation for high performance systems

Abstract: The development of scalable architectures at store levels of a layered model has concentrated on processor parallelism balanced against scalable memory bandwidth, primarily through distributed memory structures of one kind or another. A great deal of attention has been paid to hiding the distribution of memory to produce a single store image across the memory structure. It is unlikely that the distribution and concurrency aspects of scalable computing can be completely hidden at that level. This paper argues for a store layer which respects the need for caching and replication, and to do so at an "object" level granularity of memory use. These facets are interrelated through atomic processes, leading to an interface for the store which is strongly transactional in character. The paper describes the experimental performance of such a layer on a scalable multi-computer architecture. The behaviour of the store supports the view that a scalable cached "transactional" store architecture is a practical objective for high performance based on parallel computation across distributed memories.

Transactional active memory

Abstract: Advances in VLSI technology have rendered the implementation of complex operation sequences or transactions inside the body of hardware memory chips a concrete possibility. We show that such an implementation will provide an attractive performance gain and demonstrate the effectiveness through simulation.