Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Staged Software Transactional Memory

Abstract: A new form of software transactional memory based on maps for which data goes through three stages. Updates to shared memory are first redirected to a transaction-private map which associates each updated memory location with its transaction-private value. Maps are then added to a shared queue so that multiple versions of memory can be used concurrently by running transactions. Maps are later removed from the queue when the updates they refer to have been applied to the corresponding memory locations. This design offers a very simple semantic where starting a transaction takes a stable snapshot of all transactional objects in memory. It prevents transactions from aborting or seeing inconsistent data in case of conflict. Performance is interesting for long running transactions as no synchronization is needed between a transaction's start and commit, which can themselves be lock free.

Concurrent GC leveraging transactional memory

Abstract: We predict that the ever-growing number of cores on our desktops will require a re-examination of concurrent programming. Two technologies are likely to become mainstream in response: Transactional memory provides a superior programming model to traditional lock-based concurrency, while Concurrent GC can take advantage of multiple cores to eliminate perceptible pauses in desktop applications such as games or Internet telephony. This paper proposes a combination of the two technologies, producing a synergy that improves scalability while eliminating the annoyance of user-perceivable pauses.Specifically, we show how concurrent GC can share some of the mechanisms required for transactional memory. Thus as transactional memory becomes more efficient, so too will concurrent GC. We demonstrate how, using a state of the art software transactional memory system, we can build a state of the art concurrent collector. Our goal was to reduce 90% of pause times to under one millisecond. Of the remainder, we aim for 90% to be under 10ms, and90% of those left to be under 100ms. Our performance results show that we were able to achieve these targets, with pause times between one or two orders of magnitude lower than mainstream technologies.

Fast read sharing mechanism for software transactional memory

Abstract: Current multiprocessor architectures do not support synchronization primitives that can atomically access multiple memory locations. Software transactional memory (STM) aims to provide this functionality in software. With STM, a thread uses a transaction to access multiple memory locations, and then tries to commit the transaction. The transaction’s operations either take effect atomically when the transaction commits, or do not take effect at all. Part of committing a transaction involves “validating” the transaction, that is confirming that none of the locations it accesses have changed during the transaction. In many cases, it is also important to validate a transaction repeatedly during its execution in order to avoid incorrect behavior due to the transaction observing inconsistent state. In all kinds of STM, it is desirable to allow concurrent transactions to read memory locations in common, without causing each other to abort. Support for this functionality is called ”read sharing”. Current STM algorithms do not support read sharing in an efficient way: the simple algorithms suffer from slow validation, while more complex approaches impose a high performance penalty both for a transaction reading a location and for a transaction writing to a location which is currently being read by multiple other transactions. This paper presents an efficient new read sharing mechanism, which can be easily integrated into most current STM implementations. Our new mechanism is simple, and imposes a minimal cost on transactional read and write operations, while substantially reducing the average cost of validating transactions.

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency

Abstract: Scaling of semiconductor devices has enabled higher levels of integration and performance improvements at the price of making devices more susceptible to the effects of static and dynamic variability. Adding safety margins (guardbands) on the operating frequency or supply voltage prevents timing errors, but has a negative impact on performance and energy consumption. We propose Edge-TM, an adaptive hardware/software error management policy that (i) optimistically scales the voltage beyond the edge of safe operation for better energy savings and (ii) works in combination with a Hardware Transactional Memory (HTM)-based error recovery mechanism. The policy applies dynamic voltage scaling (DVS) (while keeping frequency fixed) based on the feedback provided by HTM, which makes it simple and generally applicable. Experiments on an embedded platform show our technique capable of 57% energy improvement compared to using voltage guardbands and an extra 21-24% improvement over existing state-of-the-art error tolerance solutions, at a nominal area and time overhead.

Hint instruction for managing transactional aborts in transactional memory computing environments

Abstract: When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.