Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

A hardware/software framework for supporting transactional memory in a MPSoC environment

Abstract: Manufacturers are focusing on multiprocessor-system-on-a-chip (MPSoC) architectures in order to provide increased concurrency, rather than increased clock speed, for both large-scale as well as embedded systems Traditionally lock-based synchronization is provided to support concurrency; however, managing locks can be very difficult and error prone In addition, the performance and power cost of lock-based synchronization can be high Transactional memories have been extensively investigated as an alternative to lock-based synchronization in general-purpose systems It has been shown that transactional memory has advantages over locks in terms of ease of programming, performance and energy consumption However, their applicability to embedded multi-core platforms has not been explored yet In this paper, we demonstrate a complete hardware transactional memory solution for an embedded multi-core architecture, consisting of a cache-coherent ARM-based cluster, similar to ARM's MPCore Using cycle accurate power and performance models for the transactional memory hardware, we evaluate our architectural framework over a set of different system and application settings, and show that transactional memory is a promising solution, even for resource-constrained embedded multiprocessors

Clock gate on abort: Towards energy-efficient hardware Transactional Memory

Abstract: Transactional Memory (TM) is an emerging technology which promises to make parallel programming easier compared to earlier lock based approaches. However, as with any form of speculation, Transactional Memory too wastes a considerable amount of energy when the speculation goes wrong and transaction aborts. For Transactional Memory this wastage will typically be quite high because programmer will often mark a large portion of the code to be executed transactionally[4].

Transaction Chopping for Parallel Snapshot Isolation

Abstract: Modern Internet services often achieve scalability and availability by relying on large-scale distributed databases that provide consistency models for transactions weaker than serialisability. We investigate the classical problem of transaction chopping for a promising consistency model in this class--parallel snapshot isolation PSI, which weakens the classical snapshot isolation to allow more efficient large-scale implementations. Namely, we propose a criterion for checking when a set of transactions executing on PSI can be chopped into smaller pieces without introducing new behaviours, thus improving efficiency. We find that our criterion is more permissive than the existing one for chopping serialisable transactions. To establish our criterion, we propose a novel declarative specification of PSI that does not refer to implementation-level concepts and, thus, allows reasoning about the behaviour of PSI databases more easily. Our results contribute to building a theory of consistency models for modern large-scale databases.

Exception ordering in contention management to support speculative sequential semantics

Abstract: Various technologies and techniques are disclosed for handling exceptions in sequential statements that are executed in parallel. A transactional memory system is provided with a contention manager. The contention manager is responsible for managing exceptions that occur within statements that were designed to be executed in an original sequential order, and that were transformed into ordered transactions for speculative execution in parallel. The contention manager ensures that any exceptions that are thrown from one or more speculatively executed blocks while the statements are being executed speculatively in parallel are handled in the original sequential order.

Read sharing using global conflict indication and semi-transparent reading in a transactional memory space

Abstract: It has been discovered that globally indicating read-write conflicts and semi-transparent read sharing in a transactional memory space allows for a more expedient validation. Without being aware of particular transactions, a writing transaction can determine that a read-write conflict will occur with some transaction that has read one or more memory locations to be modified by the writing transaction. With semi-transparent reading, reading transactions can validate quickly. If a read-write conflict has not occurred since a reading transaction began (or since the last validation), then the previous reads are valid. Otherwise, the reading transaction investigates each memory location or ownership record to determine if a read-write conflict affected the investigating transaction.