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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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Patent
29 Jun 2009
TL;DR: In this article, the authors present a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system, and detects a transaction failure associated with the transaction.
Abstract: One embodiment provides a system that facilitates the execution of a transaction for a program in a hardware-supported transactional memory system. During operation, the system records a misspeculation indicator of the transaction during execution of the transaction using hardware transactional memory mechanisms. Next, the system detects a transaction failure associated with the transaction. Finally, the system provides the recorded misspeculation indicator to the program to facilitate a response to the transaction failure by the program.

18 citations

Proceedings ArticleDOI
25 Jul 2010
TL;DR: View transactions are presented, a model for relaxed consistency checks in software transactional memory (STM) that is simpler to reason about, provide opacity and maintain composability, and outperform the prior approaches by 1.13x to 2x on various benchmarks.
Abstract: We present view transactions, a model for relaxed consistency checks in software transactional memory (STM). View transactions always operate on a consistent snapshot of memory but may commit in a different snapshot. They are therefore simpler to reason about, provide opacity and maintain composability. In addition, view transactions avoid many of the overheads associated with previous approaches for relaxing consistency checks. As a result, view transactions outperform the prior approaches by 1.13x to 2x on various benchmarks.

18 citations

Journal ArticleDOI
TL;DR: It is shown that HTM allows for achieving nearly lock-free processing of database transactions by carefully controlling the data layout and the access patterns, and provides a scalable, powerful, and easy to use synchronization primitive.
Abstract: So far, transactional memory—although a promising technique—suffered from the absence of an efficient hardware implementation. Intel’s Haswell microarchitecture introduced hardware transactional memory (HTM) in mainstream CPUs. HTM allows for efficient concurrent, atomic operations, which is also highly desirable in the context of databases. On the other hand, HTM has several limitations that, in general, prevent a one-to-one mapping of database transactions to HTM transactions. In this work, we devise several building blocks that can be used to exploit HTM in main-memory databases. We show that HTM allows for achieving nearly lock-free processing of database transactions by carefully controlling the data layout and the access patterns. The HTM component is used for detecting the (infrequent) conflicts, which allows for an optimistic, and thus very low-overhead execution of concurrent transactions. We evaluate our approach on a four-core desktop and a 28-core server system and find that HTM indeed provides a scalable, powerful, and easy to use synchronization primitive.

18 citations

Proceedings ArticleDOI
26 Jan 2017
TL;DR: Evaluation using key-value store benchmarks on a 20-core HTM-capable multi-core machine shows that Eunomia leads to 5X-11X speedup under high contention, while incurring small overhead under low contention.
Abstract: While hardware transactional memory (HTM) has recently been adopted to construct efficient concurrent search tree structures, such designs fail to deliver scalable performance under contention. In this paper, we first conduct a detailed analysis on an HTM-based concurrent B+Tree, which uncovers several reasons for excessive HTM aborts induced by both false and true conflicts under contention. Based on the analysis, we advocate Eunomia, a design pattern for search trees which contains several principles to reduce HTM aborts, including splitting HTM regions with version-based concurrency control to reduce HTM working sets, partitioned data layout to reduce false conflicts, proactively detecting and avoiding true conflicts, and adaptive concurrency control. To validate their effectiveness, we apply such designs to construct a scalable concurrent B+Tree using HTM. Evaluation using key-value store benchmarks on a 20-core HTM-capable multi-core machine shows that Eunomia leads to 5X-11X speedup under high contention, while incurring small overhead under low contention.

18 citations

Proceedings ArticleDOI
Marc Tremblay1
12 Aug 2007
TL;DR: In his role, Tremblay sets future directions for Sun’s processor and system roadmap, incorporating techniques he has helped develop over the past several years, including; Chip Multiprocessing, Chip Multithreading, speculative multith Reading, assist threading and Transactional Memory.
Abstract: Bio Dr. Marc Tremblay is a Sun Fellow, Senior Vice President, and CTO for Sun’s Microelectronics Group. In his role, Tremblay sets future directions for Sun’s processor and system roadmap. His mission is to move the entire product line to the Throughput Computing paradigm, incorporating techniques he has helped develop over the past several years, including; Chip Multiprocessing, Chip Multithreading, speculative multithreading, assist threading and Transactional Memory. Prior to his current position, he was co-architect for Sun’s UltraSPARC I, the MDR Microprocessor of the Year in 1995, and chief architect for the UltraSPARC II microprocessor. He was also the chief architect for the MAJC Program, which was nominated for best emerging technology in 1999 and best media processor in 2000 by MDR Analysts. He also started and architected the picoJava processor core, a Java bytecode engine. Tremblay holds a M.S. and Ph.D. in Computer Science from UCLA and a B.S. in Physics Engineering from Laval University in Canada. He holds over 121 US patents in various areas of computer architecture. Tremblay was nominated for Innovator of the year by EDN Magazine in 1999. He was the Co-Chair of the Hot Chips 2000 Conference and delivered the keynote address for The 31st Annual International Symposium on Computer Architecture (ISCA 2004) in Munich, Germany. He taught a graduate course on computer architecture at Stanford in 2002.Tremblay is a member of IEEE and ACM.

18 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888