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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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Book ChapterDOI
Qi Shen1, Craig Sharp1, William Blewitt1, Gary Ushaw1, Graham Morgan1 
24 Aug 2015
TL;DR: This paper is the first to provide results comparing GPU based STMs with a CPU based STM, and demonstrates competitive performance results in comparison with existing STMs for both the GPU and CPU.
Abstract: In this paper we describe an implementation of a software transactional memory library for the GPU written in CUDA. We describe the implementation of our transaction mechanism which features both tentative and regular locking along with a contention management policy based on a simple, yet effective, static priority rule called Priority Rule Software Transactional Memory (PR-STM). We demonstrate competitive performance results in comparison with existing STMs for both the GPU and CPU. While GPU comparisons have been studied, to the best of our knowledge we are the first to provide results comparing GPU based STMs with a CPU based STM.

15 citations

Proceedings ArticleDOI
14 May 2013
TL;DR: FaulTM-multi, a fault tolerance scheme for multi threaded applications running on transactional memory hardware which reduces the performance degradation of lockstepping and creates 28% less checkpoints compared to Rebound, the state of the art checkpointing scheme.
Abstract: Providing fault tolerance especially to mission critical applications in order to detect transient and permanent faults and to recover from them is one of the main necessity for processor designers. However, fault tolerance for multi-threaded applications presents high performance degradations due to comparing the results of the instruction streams, checkpointing the entire system and recovering from the detected errors to an agreed state. In this study, we present FaulTM-multi, a fault tolerance scheme for multi threaded applications running on transactional memory hardware which reduces these performance degradations. FaulTM-multi decreases the performance degradation of lockstepping, a conventional fault detection scheme, from 23% and 9% to 10% and 2% for lock-based parallel and TM applications respectively. Also, FaulTM-multi creates 28% less checkpoints compared to Rebound, the state of the art checkpointing scheme.

15 citations

01 Jan 2014
TL;DR: This work presents the first precise race detection tool that improves race-detection slowdown by using commercial hardware transactional memory support to synchronize analysis and program data and obtains noteworthy speedups over lock-based protection of race analysis metadata.
Abstract: It is typical for state-of-the-art dynamic race detection algorithms for C programs to slow down an application by a large factor. Our measurements indicate that a significant portion of this slowdown is due to additional lock-based synchronization performed by instrumentation code. This synchronization is necessary to ensure atomic update of analysis state. We present the first precise race detection tool that improves race-detection slowdown by using commercial hardware transactional memory support to synchronize analysis and program data. By careful choice of transaction sizes, we obtain noteworthy speedups over lock-based protection of race analysis metadata.

15 citations

Patent
15 Dec 2009
TL;DR: Using cache resident transaction hardware to accelerate a software transactional memory system is discussed in this article, where the authors identify a plurality of atomic operations intended to be performed by a transactional system as transactional operations as part of a software transaction.
Abstract: Using cache resident transaction hardware to accelerate a software transactional memory system. The method includes identifying a plurality of atomic operations intended to be performed by a software transactional memory system as transactional operations as part of a software transaction. The method further includes selecting at least a portion of the plurality of atomic operations. The method further includes attempting to perform the portion of the plurality of atomic operations as hardware transactions using cache resident transaction hardware.

15 citations

Proceedings ArticleDOI
14 Mar 2007
TL;DR: A novel nonblocking word-based STM is presented based on Ennals's argument that nonblocking STMs cannot store datain-place as most blocking STMs do, which eliminates several significant sources of common-case overhead in the previous best non blocking word based STM, and performs comparably with the simple blocking STM on which it is based.
Abstract: Foundational transactional memory research grew out of research into nonblocking concurrent data structures, which aim to overcome the many well-known software engineering, performance, and robustness problems associated with lock-based implementations. Recently, many researchers have developed blocking STMs, recognising that they are much easier to design and that the software engineering benefits of STM can be delivered even by a blocking STM. But hiding blocking from the application programmer does not eliminate all of its disadvantages, and in some cases blocking is unacceptable, for example if STM is to be used to coordinate between an interrupt handler and the interrupted thread.Recently, a common belief has emerged that blocking STMs are fundamentally faster than nonblocking ones largely based on Ennals's argument [2] that nonblocking STMs cannot store datain-place as most blocking STMs do. However, this argument is based only on intuition, not a formal proof. It misses the possibility of nonblocking STM designs that closely mimic blocking STMs in the common case, resorting to techniques such as displacing transactional data only when needed to avoid waiting for a thread that is delayed while modifying it.We present a novel nonblocking word-based STM based on this approach. Our STM eliminates several significant sources of common-case overhead in the previous best nonblocking word based STM, and also performs comparably with the simple blocking STM on which it is based.

15 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888