Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Investigating transactional memory performance on ccNUMA machines

Abstract: Most Software Transactional Memory (STM) research has focused on multi-core processors and small SMP machines; limited research has been aimed at the clusters, leaving the area of big SMP machines unexplored. Big SMP machine usually use Non-Uniform Memory Access (NUMA) to unburden the overloading between CPUs and the memory. In this paper, we evaluate several STM implementations on big SMP machine with cache coherent NUMA (ccNUMA) architecture. We found the remote memory access latency is the key factor influencing the STM performance. We also analyze the different design choices of STM. Finally, we conclude a specific design choice to achieve high performance in this domain.

Transactional Memory System

Abstract: A transactional memory system is described for reporting memory access violations which occur when memory accesses made from instructions within a transaction conflict with memory accesses to the same memory location made from a non-transactional instruction. In an embodiment this is achieved by creating two mappings of a physical heap being used by a thread. The thread (which may be part of a multi-threaded process) comprises instructions for both transactional and non-transactional accesses to the physical heap which may execute concurrently as part of that thread. One of the mappings is used for non-transactional memory accesses to the physical heap. The other mapping is used for transactional memory accesses to the physical heap. Access permissions associated with the mappings are controlled to enable attempted memory access violations to be detected and reported.

Prettier concurrency: purely functional concurrent revisions

Abstract: This article presents an extension to the work of Launchbury and Peyton-Jones on the ST monad. Using a novel model for concurrency, called concurrent revisions [3,5], we show how we can use concurrency together with imperative mutable variables, while still being able to safely convert such computations (in the Rev monad) into pure values again.In contrast to many other transaction models, like software transactional memory (STM), concurrent revisions never use rollback and always deterministically resolve conflicts. As a consequence, concurrent revisions integrate well with side-effecting I/O operations. Using deterministic conflict resolution, concurrent revisions can deal well with situations where there are many conflicts between different threads that modify a shared data structure. We demonstrate this by describing a concurrent game with conflicting concurrent tasks.

Automatic function call in multithreaded application

Abstract: In general, in one aspect, the disclosure describes a method to detect a transaction and direct non transactional memory (TM) user functions within the transaction. The non TM user functions are treated as TM functions and added to the TM list.

SymptomTM: Symptom-Based Error Detection and Recovery Using Hardware Transactional Memory

Abstract: Fault-tolerance has become an essential concern for processor designers due to increasing transient and permanent fault rates. In this study we propose Symptom TM, a symptom-based error detection technique that recovers from errors by leveraging the abort mechanism of Transactional Memory (TM). To the best of our knowledge, this is the first architectural fault-tolerance proposal using Hardware Transactional Memory (HTM). Symptom TM can recover from 86% and 65% of catastrophic failures caused by transient and permanent errors respectively with no performance overhead in error-free executions.