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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


Papers
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Book ChapterDOI
09 Jun 2009
TL;DR: An existing analytic framework for modeling software transactional memory (STM) is extended to an optimistic STM variant in which write locks are acquired lazily, which helps to predict STM performance trends as the number of cores on multi-processors increases, but other performance trends provide additional insight into system behavior.
Abstract: We extend an existing analytic framework for modeling software transactional memory (STM) to an optimistic STM variant in which write locks are acquired lazily. Lazy locking requires a different calculation of the transition probabilities of the underlying discrete-time Markov chain (DTMC). Based on few relevant input parameters, like the number of concurrent transactions, the transaction lengths, the share of writing operations and the number of accessible transactional data ojects, a fixed-point iteration over closed-form analytic expressions delivers key STM performance measures, e.g., the mean number of transaction restarts and the mean number of processed steps of a transaction. In particular, the analytic model helps to predict STM performance trends as the number of cores on multi-processors increases, but other performance trends provide additional insight into system behavior.

9 citations

Patent
25 Oct 2006
TL;DR: In this paper, the authors present a debugging tool for transactional programming using transactional memory implemented in hardware, software, and a mixture of the two types of hardware and software.
Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, various features and capabilities for debugging programs executed using transactional memory are absent from conventional debuggers. Because transactional memory implementations provide the “illusion” of multiple memory locations changing value atomically, there are challenges involved with integrating debuggers with such programs to provide the user with a coherent view of program execution. For instance, when execution is halted for debugging, a user may request to view a transactional variable or memory location. The transactional variable or memory location may have a pre-transaction value and a tentative value. Allowing a user to only view one of the values reduces the capacity of a user to reason about the behavior of the code.

9 citations

01 Jan 2014
TL;DR: This paper presents a source-to-source transformation which augments the program with an encoding of the SI semantics, and proves that verifying the resulting program with transformed user annotations and specifications is equivalent to verifying the original transactional program running under SI.
Abstract: We present a static verification approach for programs running under snapshot isolation (SI) and similar relaxed transactional semantics. Relaxed conflict detection schemes such as snapshot isolation (SI) are used widely. Under SI, transactions are no longer guaranteed to be serializable, and the simplicity of reasoning sequentially within a transaction is lost. In this paper, we present an approach for statically verifying properties of transactional programs operating under SI. Differently from earlier work, we handle transactional programs even when they are designed not to be serializable. We present a source-to-source transformation which augments the program with an encoding of the SI semantics. Verifying the resulting program with transformed user annotations and specifications is equivalent to verifying the original transactional program running under SI ‐ a fact we prove formally. Our encoding preserves the modularity and scalability of VCC’s verification approach. We applied our method successfully to benchmark programs from the transactional memory literature.

9 citations

Journal ArticleDOI
TL;DR: It is shown that there are problem instances for which there is no scheduling algorithm that can simultaneously minimize the completion time and communication cost, and these instances reveal a trade-off, minimizing execution time implies high communication cost and vice versa.
Abstract: We consider scheduling problems in the data flow model of distributed transactional memory. Objects shared by transactions move from one network node to another by following network paths. We examine how the objects’ transfer in the network affects the completion time of all transactions and the total communication cost. We show that there are problem instances for which there is no scheduling algorithm that can simultaneously minimize the completion time and communication cost. These instances reveal a trade-off, minimizing execution time implies high communication cost and vice versa. On the positive side, we provide scheduling algorithms which are independently communication cost near-optimal or execution time efficient.

9 citations

Proceedings ArticleDOI
12 Mar 2016
TL;DR: This paper presents PleaseTM, a mechanism that allows more freedom in deciding which transaction to abort, while leaving the coherence protocol design unchanged, on STAMP benchmarks running at 32 threads compared to requester-wins HTM.
Abstract: With recent commercial offerings, hardware transactional memory (HTM) has finally become an important tool in writing multithreaded applications. However, current offerings are commonly implemented in a way that keep the coherence protocol unmodified. Data conflicts are recognized by coherence messages sent by the requester to sharers of the cache block (e.g., a write to a speculatively read line), who are then aborted. This tends to abort transactions that have done more work, leading to suboptimal performance. Even worse, this can lead to live-lock situations where transactions repeatedly abort each other. In this paper, we present PleaseTM, a mechanism that allows more freedom in deciding which transaction to abort, while leaving the coherence protocol design unchanged. In PleaseTM, transactions insert plea bits into their responses to coherence requests as a simple payload, and use these bits to inform conflict management decisions. Coherence permission changes are then achieved with normal coherence requests. Our experiments show that this additional freedom can provide on average 43% speedup, with a maximum of 7-fold speedup, on STAMP benchmarks running at 32 threads compared to requester-wins HTM.

9 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888