scispace - formally typeset
Search or ask a question
Topic

Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


Papers
More filters
Proceedings ArticleDOI
20 Feb 2008
TL;DR: This paper provides a detailed performance and memory consumption analysis of the overheads of software transactional memory and transactional workloads within a production quality open source Java Runtime system and details the impact of the various performance optimizations in both workloads and the underlying runtime system.
Abstract: In this paper, we evaluate the emerging Transactional Memory (TM) area by developing a set of Java transactional memory workloads and studying their performance under a Java Software Transactional Memory (STM) system and comparing them to their lock based counterparts. We provide a detailed performance and memory consumption analysis of the overheads of software transactional memory and transactional workloads within a production quality open source Java Runtime system. Additionally, we detail the impact of the various performance optimizations in both workloads and the underlying runtime system to improving both single thread performance and scalability.

6 citations

29 Apr 2018
TL;DR: This work proposes a complete framework where an STM service is associated to a set of fully partitioned scheduling algorithms in order to improve the predictability of the system as well as guaranteeing that the timing constraints are met for all the tasks.
Abstract: The current trend in the development of recent real-time embedded systems is driven by (i) a shift from single-core to multi-core platform architectures at the hardware level; (ii) a shift from sequential to parallel programming paradigms at the software level; and finally (iii) the ever increasing demand of new functionalities (e.g. additional tasks with specific timing requirements).These trends taken together increase the complexity of the system as a whole, and have a significant impact on the type of mechanisms that are adopted in order to guarantee both the functional and non-functional correctness of the system.This holds true especially in the case where these mechanisms have to maintain the correctness of data shared between different tasks executing concurrently in parallel. The access to shared resources (e.g. main memory) on single-core systems has traditionally relied on lock-based mechanisms.At any time instant, a single task is granted an exclusive access to each shared resource.However, assuming the new settings, i.e. multi-core architectures executing a set of potentially parallel tasks sharing data, the big picture changes.Tasks executing in parallel on different cores and sharing the same data may have to compete before completing the execution.It has been proven that lock-based synchronisation approaches, which were sound in single-core context, do not to scale to multi-cores and, furthermore, they hinder the composability of the system, unfortunately. On the path to solving these issues, Software Transactional Memory (STM) based approaches have been proposed as promising candidates.By using these alternative techniques, the underlying STM service would solve the conflicts between contending tasks while maintaining data consistency, and critical sections would be executed speculatively -i.e. they are executed but if the result of the computation harms the system correctness, then changes made by the computation are reverted and the results are ignored.This way, the details on how to synchronise shared data would be hidden from the programmer, thus representing a significant advantage as compared to lock-based synchronisation techniques regarding the functional correctness of the system.Regarding the non-functional correctness instead, the use of STM based approaches in real-time systems also requires the tasks timing constraints to be met.This is due to the fact that each transaction aborting and repeating multiple times before its eventual commit incurs a timing overhead that might not be negligible and, therefore, must be taken into account to prevent deadline misses at runtime. This work considers a set of potentially parallel real-time tasks sharing data and executed on a multi-core platform.Assuming this setting, first it proposes a complete framework where an STM service is associated to a set of fully partitioned scheduling algorithms in order to improve the predictability of the system as well as guaranteeing that the timing constraints are met for all the tasks.Then, it proposes the corresponding schedulability analysis for each pair of STM and scheduling algorithms.Finally, it proposes a lightweight syntax to enrich the original Ada programming language in order to support STM for concurrent real-time applications. FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO Real-Time Software Transactional Memory António Manuel de Sousa Barros Programa Doutoral em Engenharia Electrotécnica e de Computadores Supervisor: Luís Miguel Rosário da Silva Pinho

6 citations

Proceedings ArticleDOI
20 Sep 2017
TL;DR: This paper designs a set of experiments that allow them to shed lights on the internal mechanisms used in TSX to manage conflicts among transactions and to track their readsets and writesets, and builds an analytical model of TSX focused on capturing the impact on performance of two key mechanisms.
Abstract: This paper investigates the problem of deriving a white box performance model of Hardware Transactional Memory (HTM) systems. The proposed model targets TSX, a popular implementation of HTM integrated in Intel processors starting with the Haswell family in 2013.An inherent difficulty with building white-box models of commercially available HTM systems is that their internals are either vaguely documented or undisclosed by their manufacturers. We tackle this challenge by designing a set of experiments that allow us to shed lights on the internal mechanisms used in TSX to manage conflicts among transactions and to track their readsets and writesets.We exploit the information inferred from this experimental study to build an analytical model of TSX focused on capturing the impact on performance of two key mechanisms: the concurrency control scheme and the management of transactional meta-data in the processor's caches. We validate the proposed model by means of an extensive experimental study encompassing a broad range of workloads executed on a real system.

6 citations

Proceedings ArticleDOI
02 Dec 2010
TL;DR: This paper presents a detailed analysis of the behavior of real applications on a software transactional memory system and finds that most of the data conflicts were caused by application-level optimizations such as reusing objects to reduce the memory usage.
Abstract: Transactional Memory (TM) shows promise as a new concurrency control mechanism to replace lock-based synchronization. However, there have been few studies of TM systems with real applications, and the real-world benefits and barriers of TM remain unknown. In this paper, we present a detailed analysis of the behavior of real applications on a software transactional memory system. Based on this analysis, we aim to clarify what programming work is required to achieve reasonable performance in TM-based applications. We selected three existing Java applications: (1) HSQLDB, (2) the Geronimo application server, and (3) the GlassFish application server, because each application has a scalability problem caused by lock contentions. We identified the critical sections where lock contentions frequently occur, and modified the source code so that the critical sections are executed transactionally. However, this simple modification proved insufficient to achieve reasonable performance because of excessive data conflicts. We found that most of the data conflicts were caused by application-level optimizations such as reusing objects to reduce the memory usage. After modifying the source code to disable those optimizations, the TM-based applications showed higher or competitive performance compared to lock-based applications. Another finding is that the number of variables that actually cause data conflicts is much smaller than the number of variables that can be accessed in critical sections. This implies that the performance tuning of TM-based applications may be easier than that of lock-based applications where we need to take care of all of the variables that can be accessed in the critical sections.

6 citations

Book ChapterDOI
Maurice Herlihy1
12 Dec 2007
TL;DR: This paper surveys the area, with a focus on open research problems, in which Transactional memory is a computational model in which threads synchronize by optimistic, lock-free transactions.
Abstract: Computer architecture is undergoing, if not another revolution, then a vigorous shaking-up The major chip manufacturers have, for the time being, simply given up trying to make processors run faster Instead, they have recently started shipping ”multicore” architectures, in which multiple processors (cores) communicate directly through shared hardware caches, providing increased concurrency instead of increased clock speed As a result, system designers and software engineers can no longer rely on increasing clock speed to hide software bloat Instead, they must somehow learn to make effective use of increasing parallelism This adaptation will not be easy Conventional synchronization techniques based on locks and conditions are unlikely to be effective in such a demanding environment Coarse-grained locks, which protect relatively large amounts of data, do not scale, and fine-grained locks introduce substantial software engineering problems Transactional memory is a computational model in which threads synchronize by optimistic, lock-free transactions This synchronization model promises to alleviate many (perhaps not all) of the problems associated with locking, and there is a growing community of researchers working on both software and hardware support for this approach This paper surveys the area, with a focus on open research problems

6 citations


Network Information
Related Topics (5)
Compiler
26.3K papers, 578.5K citations
87% related
Cache
59.1K papers, 976.6K citations
86% related
Parallel algorithm
23.6K papers, 452.6K citations
84% related
Model checking
16.9K papers, 451.6K citations
84% related
Programming paradigm
18.7K papers, 467.9K citations
83% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888