Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Safety and Security Framework for Exception Handling in Concurrent Programming

Abstract: Exception handling mechanism provides a structured way of handling errors in software applications as compared to traditional error handling. Moreover it may cause safety and security threats if not used carefully. Some of the possible issues are information leakage, spoofed parent classes and inconsistent states. Unfortunately most programmers are rarely aware of exception handling re-percussions, in case of inappropriate exception handling. However, with the advent of multi-core processors people are more interested in utilizing all the computational powers of machine by using concurrent programming. This also brings up new challenges in terms of exception handling decisions like retry, continuation, rollback, termination and at the same time maintaining the clean state of the program. In this paper we propose a safety and security architecture by using Aspect Oriented Programming (AOP) technique and transactional memory (TM) concept without making any modifications to the development language.

On the Performance of Commit-Time-Locking Based Software Transactional Memory

Abstract: Compared with lock-based synchronization techniques, Software Transactional Memory (STM) can significantly improve the programmability of multithreaded applications. Existing research results have demonstrated through experiments that current STM designs have slower execution speed than the locks. This paper develops a theoretical explanation for the performance difference. In particular, commit-time-locking (CTL) based STMs are analyzed. A queuing theory based statistical model is developed to quantify the performance of lock-based and STM-based schemes. Analytical results obtained from the model are validated by simulations. Our study shows that (1) lock-based synchronization outperforms CTL-based STMs, and (2) when the contention level becomes low, locks and CTL-based STMs exhibit similar performance. Furthermore, we show that the performance of CTL-based STMs is sensitive to the number of threads, transaction issue rate, and bandwidth of the interconnect. Our results are expected to be useful in the early stages of designing parallel programs, especially on the selection of design schemes for STMs.

Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers

Abstract: Minimizing code duplication in an unbounded transactional memory system. A computing apparatus including one or more processors in which it is possible to use a set of common mode-agnostic TM barrier sequences that runs on legacy ISA and extended ISA processors, and that employs hardware filter indicators (when available) to filter redundant applications of TM barriers, and that enables a compiled binary representation of the subject code to run correctly in any of the currently implemented set of transactional memory execution modes, including running the code outside of a transaction, and that enables the same compiled binary to continue to work with future TM implementations which may introduce as yet unknown future TM execution modes.

Preparing Relational Algebra for “Just Good Enough” Hardware

Abstract: Device miniaturization is pointing towards tolerating imperfect hardware provided it is “good enough”. Software design theories will have to face the impact of such a trend sooner or later.