Topic
Transactional memory
About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.
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29 Nov 2010
TL;DR: The results show that symbolic prefetching combined with caching can eliminate an average of 87% of remote reads, and the approach was designed to hide the latency of accessing remote objects in distributed transactional memory and a wide range of distributed object middleware frameworks.
Abstract: Developing efficient distributed applications while managing complexity can be challenging. Managing network latency is a key challenge for distributed applications. We propose a new approach to prefetching, symbolic prefetching, that can prefetch remote objects before their addresses are known. Our approach was designed to hide the latency of accessing remote objects in distributed transactional memory and a wide range of distributed object middleware frameworks. We present a static compiler analysis for the automatic generation of symbolic prefetches--- symbolic prefetches allow objects whose addresses are unknown to be prefetched.We evaluate this prefetching mechanism in the context of a middleware framework for distributed transactional memory. Our evaluation includes microbench-marks, scientific benchmarks, and distributed benchmarks. Our results show that symbolic prefetching combined with caching can eliminate an average of 87% of remote reads. We measured speedups due to prefetching of up to 13.31 x for accessing arrays and 4.54× for accessing linked lists.
5 citations
25 Sep 2008
TL;DR: This paper analyses the problem of I/O operations within transactions, and proposes a hardware transactional memory system architecture based on multi-core processor and current cache coherent mechanisms that outperformed traditional lock-based programs.
Abstract: I/O operation within transactions is one of the challenges for hardware transactional memory. This paper analyses the problem of I/O operations within transactions, and proposes a hardware transactional memory system architecture based on multi-core processor and current cache coherent mechanisms. The system supports execution of transactions by adding transactional buffer and related hardware and software. I/O operations within transactions are implemented by partial commit based on commit-lock, and blocking / waking-up of transactional threads. The solution solves or avoids the problems that I/O operations within transactions faced, including rollback, transaction migration and transactional buffer overflow. The system has been implemented by simulation. Its performance is evaluated by five benchmark applications. Simulation results show that the transactional programs executed in our system outperformed traditional lock-based programs.
5 citations
18 Aug 2008
TL;DR: A unique invalidation algorithm is presented which boasts high transactional throughput for memory-intensive transactions and is executed through either validation or invalidation.
Abstract: Transactional memory (TM) reduces parallel programming complexity while maintaining multi-threaded performance benefits. Consistency checking, the way memory conflicts are found in TM, is critical to performance and is executed through either validation or invalidation. We present a unique invalidation algorithm which boasts high transactional throughput for memory-intensive transactions.
5 citations
03 Sep 2009
TL;DR: This paper presents two STM systems, and a formal proof for the second one is presented, which is one of the very first proofs of a STM system.
Abstract: The recent advance of multicore architectures and the deployment of multiprocessors as the mainstream computing platforms have given rise to a new concurrent programming impetus. Software transactional memories (STM) are one of the most promising approach to take up this challenge. The aim of a STM system is to discharge the application programmer from the management of synchronization when he/she has to write multiprocess programs. His/her task is to decompose his/her program in a set of sequential tasks that access shared objects, and to decompose each task in atomic units of computation. The management of the required synchronization is ensured by the associated STM system. This paper presents two STM systems, and a formal proof for the second one. Such a proof -that is not trivial- is one of the very first proofs of a STM system. In that sense, this paper strives to contribute to the establishment of theoretical foundations for STM systems.
5 citations
28 Dec 2009
TL;DR: In this study, software transactional memory systems for Multicore processors are reviewed according to the following aspects: transaction granularity, version management, conflict detection and synchronization.
Abstract: The transactional memory in multicore processors has been a very hot research area over past several years. Many transactional memory systems have been proposed to solve the synchronization problem of multicore processors. Software transactional memory is one of the critical methods to ease parallel programming and improve the scalability in the environment with many cores. In this study, software transactional memory systems for Multicore processors are reviewed according to the following aspects: transaction granularity, version management, conflict detection and synchronization. Finally, we discuss an active research challenge: whether strong isolation should be supported for the tradeoff between performance and semantics correctness in software transactional memory systems. KeywordsSoftware; Synchronization; Transactional Memory; Multicore processor; Parallel programming
5 citations