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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


Papers
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Book ChapterDOI
31 Aug 2010
TL;DR: This paper proposes a transparent technique that adaptively manages conflict unit sizes for distributed optimistic synchronization in order to relieve application developers from reasoning about such sharing phenomena.
Abstract: Distributed and parallel applications often require accessing shared data. Distributed transactional memory is an emerging concept for concurrent shared data access. By using optimistic synchronization, transactional memory is simpler to use and less error-prone than explicit lock-based synchronization. However, distributed transactional memories are particularly sensitive to phenomena such as true sharing and false sharing, which are caused by correlated data access patterns on multiple nodes. In this paper, we propose a transparent technique that adaptively manages conflict unit sizes for distributed optimistic synchronization in order to relieve application developers from reasoning about such sharing phenomena. Experiments with micro-benchmarks and an on-line data processing application similar to Twitter (using the MapReduce computing model) show the benefits of the proposed approach.

4 citations

Posted Content
TL;DR: This paper presents a sound and complete method, based on coarse-grained abstraction, for reducing proofs of opacity to the relatively simpler correctness condition: linearizability.
Abstract: Transactional memory is a mechanism that manages thread synchronisation on behalf of a programmer so that blocks of code execute with an illusion of atomicity. The main safety criterion for transactional memory is opacity, which defines conditions for serialising concurrent transactions. Proving opacity is complicated because it allows concurrent transactions to observe distinct memory states, while TM implementations are typically based on one single shared store. This paper presents a sound and complete method, based on coarse-grained abstraction, for reducing proofs of opacity to the relatively simpler correctness condition: linearizability. We use our methods to verify TML and NORec from the literature and show our techniques extend to relaxed memory models by showing that both are opaque under TSO without requiring additional fences. Our methods also elucidate TM designs at higher level of abstraction; as an application, we develop a variation of NORec with fast-path reads transactions. All our proofs have been mechanised, either in the Isabelle theorem prover or the PAT model checker.

4 citations

DOI
01 Jul 2013
TL;DR: This paper evaluates TM implementations of two algorithmic variations of the wide-spread conjugate gradients method regarding their performance on multi-core CPUs employing TM and shows that the main bottleneck for both is the waiting times at barriers.
Abstract: Transactional Memory (TM) offers new possibilities for algorithmic design. This paper evaluates TM implementations of two algorithmic variations of the wide-spread conjugate gradients method (CG) regarding their performance on multi-core CPUs employing TM. Through applying tools for TM that visualize the TM application behavior, we show that the main bottleneck for both is the waiting times at barriers and illustrate the implementation of reduction operations with TM in a beneficial way. Performance monitoring through using the PAPI interface uncovers the quantity and type of instructions that each algorithms requires. This basic work is the key for environment-aware numerics as well as a hint for software developers who plan to use TM.

4 citations

Patent
Yi Liu, Mingyu Wu, Xin Zhang, He Li, Cui Zhang 
10 Oct 2012
TL;DR: In this article, the authors propose a method for blocking and awakening transaction threads in a hardware transactional memory system, which comprises the following steps of: arranging a transaction thread register in transaction supporting hardware and recording an identifier of a currently-executed transaction thread in the transactional thread register; when a blocked transaction thread is rescheduled and re-execussed and if the blocked thread is the same as the thread identifier in the register, continuing to submit the transaction; and if a blocked thread identifier is different from the registered transaction thread identifier, clearing a current transaction field and re
Abstract: The invention discloses a method for blocking and awakening transaction threads in a hardware transactional memory system, which comprises the following steps of: arranging a transaction thread register in transaction supporting hardware and recording an identifier of a currently-executed transaction thread in the transaction thread register; when a blocked transaction thread is rescheduled and re-executed and if the blocked transaction thread is the same as the thread identifier in the register, continuing to submit the transaction; and if the blocked transaction thread is different from the thread identifier in the register, clearing a current transaction field and re-executing the transaction The method of the invention has the advantages of eliminating the limitation that the transactions in the hardware transactional memory system are necessarily executed in a time slice, solving the problem that a transaction cache is difficult to migrate and optimizing the high-efficiency execution of the transactions in the hardware transactional memory system

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888