Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Starvation-free commit arbitration policies for transactional memory systems

Abstract: In transactional memory systems like TCC, unordered transactions are committed on a first-come, first-serve basis. If a transaction has read data that has been modified by the next transaction to commit, it will have to roll-back and a lot of computations can potentially be wasted. Even worse, such simple commit arbitration policies are prone to starvation; in fact, the performance of Raytrace in SPLASH-2 suffered significantly because of this.This paper analyzes in detail the design issues for commit arbitration policies and proposes novel policies that reduce the amount of wasted computation due to roll-back and, most importantly, avoid starvation. We analyze in detail how to incorporate them in a TCC-like transactional memory protocol. We find that our proposed schemes have no impact on the common-case performance. In addition, they add modest complexity to the baseline protocol.

Profiling Patterns of Bit Flipping for Software Transactional Memories

Abstract: Software Transactional Memory (STM) is a synchronization method proposed as an alternative to lockbased synchronization. It provides a higher-level abstraction that is easier to program, and that enables software composition. Transactions are defined by programmers, but the runtime system is responsible for detecting conflicts and avoiding race conditions. Phase Change Memory (PCM) is a new technology that is being developed to replace Dynamic Random Access Memories (DRAMs) in large datacenters. PCM write operations are much more expensive than reads in both energy and time. In this paper, we analyze performance, energy consumption, and write patterns in software transactional memories (STMs) to determine the potential of optimization for PCM scenarios. As the write operations are more expensive both in time and energy in PCMs, benchmarks from the STAMP suite were instrumented to count bits swapped due to store instructions, and experiments were executed using TinySTM. Our results showed a pattern of few bits being flipped for each memory write, and performance was inversely proportional to the number of writes. For most benchmarks, there was a small increase in energy consumption with more threads, which may be explained by the timid contention manager used by TinySTM.

Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

Abstract: In the search for new paradigms to simplify multithreaded programming, Transactional Memory (TM) is currently being advocated as a promising alternative to deadlock-prone lock-based synchronization. In this way, future many-core CMP architectures may need to provide hardware support for TM. On the other hand, power dissipation constitutes a first class consideration in multicore processor designs. In this work, we propose Selective Dynamic Serialization (SDS) as a new technique to improve energy consumption without degrading performance in applications with conflicting transactions by avoiding wasted work due to aborted transactions. Our proposal, which is implemented on top of a hardware transactional memory (HTM) system with an eager conflict management policy, detects and serializes conflicting transactions dynamically (at run-time). In its simplest form, in case of conflict, one transaction is allowed to continue whilst the rest are completely stalled. Once the executing transaction has finished, it wakes up several of the stalling transactions. More elaborated implementations of SDS try to delay this behavior until serialization of transactions is profitable, achieving the best trade-off between performance, energy savings and network traffic. SDS implementations differ from each other in the condition that triggers the serialization mode. We have evaluated several SDS schemes using GEMS, a full-system simulator implementing the LogTM-SE Eager---Eager HTM system, and several benchmarks from the STAMP suite. Results for a 16-core CMP show that SDS obtains reductions of 6 % on average in energy consumption (more than 20 % in high contention scenarios) in a wide range of benchmarks without affecting, on average, execution time. At the same time, network traffic level is also reduced by 22 %.

Specification Analysis of Transactional Memory using ITL and AnaTempura

Abstract: Transactional memory (TM) is a promising lockfree technique that offers a high-level abstract parallel programming model for future chip multiprocessor (CMP) systems. Moreover it adapts the popular well established paradigm of transaction, thus providing a general and flexible way of allowing programs to atomically read and modify disparate memory locations as a single operation. In this paper, we propose a general and executable specification model for an abstract TM with validation for various correctness conditions of concurrent transactions. This model is constructed within a flexible transition framework that allows the testing of a TM model with animation. Interval Temporal Logic (ITL) and its programming language subset AnaTempura are used to build, execute, and validate this model. To demonstrate this work, we selected a queue example to be executed and illustrated with animation.

Towards Transactional Memory for Real-Time Systems

Abstract: In this paper, we explore a new synchronization paradigm for real-time systems: transactional memory for real-time systems. Transactional memory is considered as a solution for parallel programs on a shared memory chip multiprocessor. It simplifies the programming model and increases the average case throughput. However, in real-time systems we are interested in the worst-case execution time. In this paper we show that for a periodic thread model the maximum number of transaction aborts can be bounded and the system is time predictable. Furthermore, we propose a possible hardware implementation in the context of a Java processor and show first results in a multiprocessor simulation.