Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Estimating transaction execution times for a software transactional memory

Abstract: Over the last two decades, researchers developed many software, hardware, and hybrid Transactional Memories (TMs) with various APIs and semantics. However, reduced performance when exposed to high contention loads is still the major downside of all the TMs. Although many strategies and methods have been proposed, contention management and transaction scheduling still remains an open area of research. An important piece of unsolved contention management puzzle is plausible transaction execution time estimation. In this paper we proposed two methods for estimating transaction execution times, namely the method based on log-normal distribution and the method based on gamma distribution. Experimental results presented in this paper indicate that the method based on log-normal distribution has better estimation accuracy than the method based on gamma distribution. Even more importantly, the method based on log-normal distribution uses 10 times shorter sliding windows and its complexity is much lower than for the method based on gamma distribution, thus it is faster and requires less electrical power.

Snapshot Isolation Anomalies Detection in Software Transactional Memory

Abstract: Some performance issues of transactional memory are caused by unnecessary abort situations where non serializable and yet non con- flicting transactions are scheduled to execute concurrently. Smartly relaxing the isolation properties of transactions may overcome these issues and attain considerable performance improvements. How- ever, it is known that relaxing isolation restrictions may lead to runtime anomalies. In some situations, like database management systems, devel- opers may choose that compromise, hence avoiding anomalies explicitly. Memory transactions protect the state of the program, therefore execu- tion anomalies may have more severe consequences in the semantics of programs. So, the compromise between a relaxed isolation strategy and enforcing the necessary program correctness is harder to setup. The solution we devise is to statically analyse programs to detect the kind of anomalies that emerge under snapshot isolation. Our approach allows a compiler to either warn the developer about the possible snapshot isolation anomalies in a given program, or possibly inform automatic correctness strategies to ensure Serializability.

Efficient management of speculative data in hardware transactional memory systems

Abstract: Transactional memory systems promise to simplify parallel programming by avoiding deadlock, livelock, and serialization problems through optimistic, concurrent execution of code segments that potentially can have data conflicts with each other. Data conflict detection in proposed hardware transactional memory systems is done by associating a read bit with each cache block that is set when a block is speculatively read. However, since the set of blocks that have been speculatively read - the read set - has to be maintained until the transaction commits, one can often not replace a block that has been speculatively read. This leads to poor utilization of the private caches in a multi-core system. We propose a new scheme for managing the read set in hardware transactional memory systems. The novel insight is that only the addresses of the speculatively read blocks are needed for conflict detection but not the data. As a result, there is an opportunity to reduce the space needed to keep track of speculatively read blocks by B/A, where B is the block size and A is the block address. Assuming that B is 32 bytes and A is 32 bits, there is an eightfold space saving due to this. This paper presents a novel design for leveraging this opportunity and evaluates a concept that uses a Bloom filter to hash the addresses of the read set into a structure. We find that the proposed scheme utilizes the private cache more efficiently in a typical system configuration.

FASTLANE: Streamlining Transactions for Low Thread Counts

Abstract: Software transactional memory (STM) can lead to scalable implementations of concurrent programs, as the relative performance of an application increases with the number of threads that support it. However, the absolute performance is typically impaired by the overheads of transaction management and instrumented accesses to shared memory. This often leads STM-based programs with low thread counts to perform worse than a sequential, non-instrumented version of the same application. In this paper, we propose FASTLANE, a new STM system that bridges the performance gap between sequential execution and classical STM algorithms when running on few cores. FASTLANE seeks to reduce instrumentation costs and thus performance degradation in its target operation range. We introduce a family of algorithms that differentiate between two types of threads: One thread (the master) is allowed to commit transactions without aborting, thus with minimal instrumentation and management costs, while other threads (the helpers) can commit transactions only when they do not conflict with the master. Helpers thus contribute to the application progress without impairing on the performance of the master. We implement FASTLANE within a state-of-the-art STM runtime and compiler. Multiple code paths are produced for execution on a single, few, and many cores. Applications can dynamically select a variant at runtime, depending on the number of cores available for execution. Preliminary evaluation results indicate that our approach provides promising performance at low thread counts: FASTLANE almost systematically wins over a classical STM in the 2-4 threads range, and often performs better than sequential execution of the non-instrumented version of the same application. We believe that performance can still be improved by additional optimizations and tuning of the FASTLANE algorithms.

Consensus Numbers of Transactional Objects

Abstract: This paper describes the ability of asynchronous shared-memory distributed systems to solve the consensus problem in a wait-free manner if processes are permitted to perform transactions on the shared memory in a single atomic action. It will be shown that transactional memory is often extremely powerful, even if weak types of shared objects are used and the transactions are short. Suppose T is a type of shared object. For any positive integer m, the transactional type trans(T,m) allows processes to perform up to m accesses to a collection of objects of type T in a transaction. The transaction may also include internal process actions that do not affect the shared memory. For any non-trivial type T, trans(T,m) can solve consensus among Ω(2m/2) processes. A stronger lower bound of Ω(2m is given for a large class of objects that includes all non-trivial read-modify-write types T. If the type T is equipped with operations that allow processes to read the state of the object without altering the state, then trans(T, 2) is capable of solving consensus among any number of processes. This paper also gives a consensus algorithm for nm-1 processes using trans(n-consensus,m) and a consensus algorithm for any number of processes that uses trans(test&set, 3).