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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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DOI
01 Jan 2010
TL;DR: A new high-level language, Relaxed Memory Language (RML), is developed for expressing concurrent algorithms with a hardware-level atomicity of instructions, whose semantics is parametrized by various relaxed memory models.
Abstract: Transactional memory (TM) has shown potential to simplify the task of writing concurrent programs. TM shifts the burden of managing concurrency from the programmer to the TM algorithm. The correctness of TM algorithms is generally proved manually. The goal of this thesis is to provide the mathematical and software tools to automatically verify TM algorithms under realistic memory models. Our first contribution is to develop a mathematical framework to capture the behavior of TM algorithms and the required correctness properties. We consider the safety property of opacity and the liveness properties of obstruction freedom and livelock freedom. We build a specification language of opacity. We build a framework to express hardware relaxed memory models. We develop a new high-level language, Relaxed Memory Language (RML), for expressing concurrent algorithms with a hardware-level atomicity of instructions, whose semantics is parametrized by various relaxed memory models. We express TM algorithms like TL2, DSTM, and McRT STM in our framework. The verification of TM algorithms is difficult because of the unbounded number, length, and delay of concurrent transactions and the unbounded size of the memory. The second contribution of the thesis is to identify structural properties of TM algorithms which allow us to reduce the unbounded verification problem to a language-inclusion check between two finite state systems. We show that common TM algorithms satisfy these structural properties. The third contribution of the thesis is our tool FOIL for model checking TM algorithms. FOIL takes as input the RML description of a TM algorithm and the description of a memory model. FOIL uses the operational semantics of RML to compute the language of the TM algorithm for two threads and two variables. FOIL then checks whether the language of the TM algorithm is included in the specification language of opacity. FOIL automatically determines the locations of fences, which if inserted, ensure the correctness of the TM algorithm under the given memory model. We use FOIL to verify DSTM, TL2, and McRT STM under the memory models of sequential consistency, total store order, partial store order, and relaxed memory order.

4 citations

01 Jan 2015
TL;DR: Energy efficiency is becoming a highly significant topic regarding modern hardware and the need for decreased energy consumption in computers and more battery life in laptops and smart-phones is becoming more significant.
Abstract: Energy efficiency is becoming a highly significant topic regarding modern hardware. The need for decreased energy consumption in our computers and more battery life in our laptops and smart-phones ...

4 citations

Book ChapterDOI
03 Jan 2012
TL;DR: This paper uses a multi-version software transactional memory system that executes JMM synchronization operations asynchronously and shows that it can guarantee correct execution according to the Java memory model (JMM) without having to stall at synchronization points.
Abstract: Synchronization in distributed systems is expensive because, in general, threads must stall to obtain a lock or to operate on volatile data. Transactional memory, on the other hand, allows speculative execution so that it can hide the latencies that are inherent to distributed systems. In this paper, we discuss how transactional memory can carry over to code that uses Java's synchronization means i.e. monitors and volatiles. We show that we can guarantee correct execution according to the Java memory model (JMM) without having to stall at synchronization points. To this end, we use a multi-version software transactional memory system that executes JMM synchronization operations asynchronously. If any such execution has violated the JMM, the transaction rolls back. As a result, only blocking operations require immediate synchronization barriers.

4 citations

Proceedings ArticleDOI
20 Oct 2009
TL;DR: The hardware issues related to Hardware Transactional Memories are reviewed and some directions for the design and implementation of such systems are proposed.
Abstract: The evolution of the consumer electronic devices leads to a consolidation of the architectures towards fairly homogeneous multiprocessor platforms. As these highly programmable architectures execute explicitly parallel programs, and until automatic parallel compilers exist, the software programmer has to expose thread (i.e. coarse grain) level parallelism to use these resources. Thread is currently a well accepted programming paradigm which relies on locks, provided by some means by the hardware, to ensure atomicity of accesses. Unfortunately, programs written with locks are hard to design and debug. A decade ago, the idea of Transactional Memories was introduced to replace locks in order to simplify programming. This paper reviews the hardware issues related to Hardware Transactional Memories and proposes some directions for the design and implementation of such systems.

4 citations

26 Nov 2010
TL;DR: The concept of transactional memory implemented within a synthesizable fabric named TMFab, containing all the requisite hardware components needed to prototype a scalable chip-multiprocessor, is used, allowing transactions to complete execution faster.
Abstract: With the performance of single-core processors approaching its limits, an increased amount of research effort is focused on chip multiprocessors (CMP). However, existing lock-based synchronization methods that are critical to performing parallel computation possess limited scalability and are inherently complex to use while programming. This thesis uses the concept of transactional memory implemented within a synthesizable fabric named TMFab, containing all the requisite hardware components needed to prototype a scalable chip-multiprocessor. Its processor independent nature enables the instantiation and use of any suitable soft-processor core inside the fabric without significant modifications to the fabric hardware. Additionally, the fabric offers scalability on account of its 3D interconnect architecture that supports die-stacking to add additional processor cores to the CMP without increasing its area footprint. The hardware transactional memory system of the fabric reduces performance overheads of transactional operations, allowing transactions to complete execution faster. TMFab is shown to provide speed up as high as 3.44x for correctly partitioned independent transactions and can be used to analyze the points of contention for conflicting transactions. The fabric was synthesized for both Field Programmable Gate Array (FPGA) as well as 90nm semi-custom targets.

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888