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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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TL;DR: This paper introduces a parameter the remainder factor m, formally derive an exact WCRT for a 2-task set on STM systems using lazy conflict detection (LCD), and proposes an exact schedulability test for a 1- task set and a new necessary condition and new sufficient condition to schedule an n- Task set.
Abstract: Software transactional memory (STM) is a transactional mechanism of controlling access to shared resources in memory. This transactional mechanism is similar to the abort-and-restart execution model in a functional reactive system (FRS). Due to its abort-and-restart nature, the execution semantics of STM are different from the classic preemptive or nonpreemptive model. Some research has strong constraints for its worst case response time (WCRT) analysis. In this paper, we research on worst case response time and schedulability analysis for real-time software transactional memory-lazy conflict detection (STM-LCD). Specifically, we introduce a parameter the remainder factor m, formally derive an exact WCRT for a 2-task set on STM systems using lazy conflict detection (LCD), propose an exact schedulability test for a 2-task set. Also, we present a near-exact WCRT for an n-task set on STM-LCD, and propose a new necessary condition and a new sufficient condition to schedule an n-task set. Finally, we show that experimental results are accordant with the aforementioned analysis.

3 citations

Journal ArticleDOI
01 Dec 2013
TL;DR: Experimental results show that partitioning shared data into separate views can improve performance when one of the views has high contention while others may have low contention, because the contention of each view is independently controlled by RAC.
Abstract: This paper extensively evaluates the performance of View-Oriented Transactional Memory (VOTM) based on two implementations that adopt different Transactional Memory (TM) algorithms. The Restricted Admission Control (RAC) mechanism in VOTM plays a key role in the performance gains of VOTM. In this paper, we use six applications to evaluate the performance advantage of VOTM. Experimental results show that partitioning shared data into separate views can improve performance when one of the views has high contention while others may have low contention, because the contention of each view is independently controlled by RAC. For memory-intensive applications, even when the contention on application data is not high enough to justify admission control by RAC, partitioning shared data into different views can improve the performance of TM systems due to the reduced contention on the metadata of the TM systems.

3 citations

Journal ArticleDOI
S. Asaad1
TL;DR: The effectiveness of the tools and methodology used to model, co-design, and validate these new features from early concept phase through design implementation of IBM Blue Gene/Q are shown, allowing the design targets at an aggressive project schedule.
Abstract: Major architectural innovations in the compute node have been introduced in the IBM Blue Gene®/Q, including programmable Level 1 (L1) cache data prefetching units to hide memory access latency, hardware support for transactional memory (TM) and speculative execution (SE), an enhanced five-dimensional integrated torus network, and a high-performance quad floating-point SIMD (single-instruction, multiple-data) unit. In this paper, we present the tools and methodology that we used to model, co-design, and validate these new features from early concept phase through design implementation. Early in the design cycle, we made extensive use of an architectural simulator, BGQSim, capable of executing unmodified binary Blue Gene/Q code for single as well as multiple nodes. As the hardware description language for the chip implementation became available, we complemented BGQSim with a cycle-accurate and cycle-reproducible, large-scale field-programmable gate array-based platform, Twinstar, to validate the implementation against performance targets and functional specifications. Through specific examples, we show the effectiveness of these tools in co-developing the hardware and software of Blue Gene/Q, allowing us to meet the design targets at an aggressive project schedule.

3 citations

01 Jan 2012
TL;DR: ByteSTM as mentioned in this paper is a virtual machine-level implementation of transactional memory (TM) for Java programs, which is based on TL2 and RingSTM and transparently supports implicit transactions.
Abstract: (ABSTRACT) As chip vendors are increasingly manufacturing a new generation of multi-processor chips called multicores, improving software performance requires exposing greater concurrency in software. Since code that must be run sequentially is often due to the need for synchronization , the synchronization abstraction has a significant effect on program performance. Lock-based synchronization – the most widely used synchronization method – suffers from programability, scalability, and composability challenges. Transactional memory (TM) is an emerging synchronization abstraction that promises to alleviate the difficulties with lock-based synchronization. With TM, code that read/write shared memory objects is organized as transactions, which speculatively execute. When two transactions conflict (e.g., read/write, write/write), one of them is aborted, while the other commits, yielding (the illusion of) atomicity. Aborted transactions are restarted , after rolling-back changes made to objects. In addition to a simple programming model, TM provides performance comparable to lock-based synchronization. Software transactional memory (STM) implements TM entirely in software, without any special hardware support, and is usually implemented as a library, or supported by a compiler or by a virtual machine. In this thesis, we present ByteSTM, a virtual machine-level Java STM implementation. ByteSTM implements two STM algorithms, TL2 and RingSTM, and transparently supports implicit transactions. Program bytecode is automatically modified to support transactions: memory load/store bytecode instructions automatically switch to transactional mode when a transaction starts, and switch back to normal mode when the transaction successfully commits. Being implemented at the VM-level, it accesses memory directly and uses absolute memory addresses to uniformly handle memory. Moreover, it avoids Java garbage collection (which has a negative impact on STM performance), by manually allocating and recycling memory for transactional metadata. ByteSTM uses field-based granularity, and uses the thread header to store transactional metadata, instead of the slower Java ThreadLocal abstraction. We conducted experimental studies comparing ByteSTM with other state-of-the-art Java STMs including Deuce, ObjectFabric, Multiverse, DSTM2, and JVSTM on a set of micro-benchmarks and macro-benchmarks. Our results reveal that, ByteSTM's transactional throughput improvement over competitors ranges from 20% to 75% on micro-benchmarks and from 36% to 100% on macro-benchmarks. Without her love, care and support, I could not have completed this thesis To my parents. Without their love, trust and continued support, I could not have made their dream true iii Acknowledgments First, I would like to thank my advisor, Dr. Binoy Ravindran, for his continues support, help, guidance, encouragement, and trust. He believed in me …

3 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888