scispace - formally typeset
Search or ask a question
Topic

Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


Papers
More filters
Patent
Gad Sheaffer1, Raikin Shlomo1, Vadim Bassin1, Raanan Sade1, Ehud Cohen1, Oleg Margulis1 
30 Dec 2008
TL;DR: In this paper, a method and apparatus for monitoring memory accesses in hardware to support transactional execution is described, which monitors accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity.
Abstract: A method and apparatus for monitoring memory accesses in hardware to support transactional execution is herein described. Attributes are monitor accesses to data items without regard for detection at physical storage structure granularity, but rather ensuring monitoring at least at data items granularity. As an example, attributes are added to state bits of a cache to enable new cache coherency states. Upon a monitored memory access to a data item, which may be selectively determined, coherency states associated with the data item are updated to a monitored state. As a result, invalidating requests to the data item are detected through combination of the request type and the monitored coherency state of the data item.

83 citations

Patent
30 Mar 2006
TL;DR: In this paper, the authors describe a mechanism to provide transactional memory execution in a virtualized mode, in which data corresponding to a transactional access request may be stored in a portion of a memory after an operation corresponding to the access request causes an overflow and a stored value may be updated for an occurrence of the overflow.
Abstract: Methods and apparatus to provide transactional memory execution in a virtualized mode are described. In one embodiment, data corresponding to a transactional memory access request may be stored in a portion of a memory after an operation corresponding to the transactional memory access request causes an overflow and a stored value may be updated for an occurrence of the overflow.

83 citations

Patent
30 Jun 2009
TL;DR: In this article, a hardware assisted transactional memory system with open nested transactions is presented, where a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional systems.
Abstract: Hardware assisted transactional memory system with open nested transactions. Embodiments include a system whereby hardware acceleration of transactions can be accomplished by implementing open nested transaction in hardware which respect software locks such that a top level transaction can be implemented in software, and thus not be limited by hardware constraints typical when using hardware transactional memory systems.

82 citations

Patent
16 Mar 2012
TL;DR: In this article, the authors present three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets, perthread conflict summary tables, which identify the threads with which conflicts have occurred, and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow.
Abstract: The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.

82 citations

01 Jan 2006
TL;DR: This work identifies TM implementations from the literature corresponding to several specific conflict and arbitration functions, and offers candidate sequential specifications to capture the semantics of transactional memory.
Abstract: Transactional memory (TM) provides a general-purpose mechanism with which to construct concurrent objects. Transactional memory can also be thought of as a concurrent object, but its semantics are less clear than those of the objects typically constructed on top of it. In particular, commit operations in a transactional memory may fail when transactions conflict. Under what circumstances, exactly, is such behavior permissible? We offer candidate sequential specifications to capture the semantics of transactional memory. In all cases, we require that reads return consistent values in any transaction that succeeds. Each specification embodies a conflict function, which specifies when two transactions cannot both succeed. Optionally, a specification may also embody an arbitration function, which specifies which of two conflicting transactions must fail. In the terminology of the STM literature, arbitration functions correspond to the concept of contention management. We identify TM implementations from the literature corresponding to several specific conflict and arbitration functions. We note that the specifications facilitate not only correctness (i.e., linearizability) proofs for nonblocking TM implementations, but also formal comparisons of the degree to which different implementations admit inter-transaction concurrency. In at least one case— eager detection of write-write conflicts and lazy detection of readwrite conflicts—the formalization exercise has led us to semantics that are arguably desirable, but not, to the best of our knowledge, provided by any current TM system.

81 citations


Network Information
Related Topics (5)
Compiler
26.3K papers, 578.5K citations
87% related
Cache
59.1K papers, 976.6K citations
86% related
Parallel algorithm
23.6K papers, 452.6K citations
84% related
Model checking
16.9K papers, 451.6K citations
84% related
Programming paradigm
18.7K papers, 467.9K citations
83% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888