Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Transaction processing method in hybrid transactional memory system and transaction processing apparatus

Abstract: Disclosed are a transaction processing method and a transaction processing system in a hybrid transactional memory system. The transaction processing method in a hybrid transactional memory system according to an embodiment of the present invention includes the steps of: performing HTM processing by a hardware transactional memory (HTM) if a transaction starts from a workload; and performing STM processing by a software transactional memory (STM) on the transaction. Accordingly, the present invention can increase the processing efficiency of a large-scale DB transaction.

Concurrent Cache-Oblivious B-Trees Using Transactional Memory

Abstract: Cache-oblivious B-trees for data sets stored in external memory represent an application that can benefit from the use of tran sactional memory (TM), yet pose several challenges for existing TM implementations. Using TM, a programmer can modify a serial, in-memory cache-oblivious B-tree (CO B-tree) to support concurrent operations in a straightforward manner, by performing queries and updates as individual transactions. In this paper, we describe three obstacles that must be overcome, however, before one can implement an efficient external-memory concurrent CO B-tre e. First, CO B-trees must perform input/output (I/O) inside a transaction if the underlying data set is too large to fit in main mem ory. Many TM implementations, however, prohibit such transaction I/O. Second, a CO B-tree that operates on persistent data requires a TM system that supports durable transactions if the programmer wishes to be able to restore the data to a consistent state after a pro gram crash. Finally, CO B-trees operations generate megalithic transactions, i.e., transactions that modify the entire data struc ture, because performance guarantees on CO B-trees are only amortized bounds. In most TM implementations, these transactions create a serial bottleneck because they conflict with all other concurrent tran sactions operating on the CO B-tree. Of these three issues, we argue that a solution for the first tw o issues of transaction I/O and durability is to use a TM system that supports transactions on memory-mapped data. We demonstrate the feasibility of this approach by using LibXac, a library t hat supports memory-mapped transactions, to convert an existing serial implementation of a CO B-tree into a concurrent version with only a few hours of work. We believe this approach can be generalized, that memory-mapped transactions can be used for other applications that concurrently access data stored in external memory.

Parallelizing Stochastic Gradient Descent with Hardware Transactional Memory for Matrix Factorization

Abstract: Rapid increase of the amount of available data necessitates large-scale machine learning methods, and Stochastic Gradient Descent (SGD) has become a predominant one of the choices. However, the inherently sequential properties of SGD severely constrain its scalability and prevent it benefiting from multi-core devices. This work parallelizes SGD with transactional memory and leverages hardware support of transactional execution to explore better use of newly deployed features in commercial multi-core processors. To evaluate the performance of our SGD implementation, we compare it with the traditional lock-based approach and conduct quantitative analysis of its synchronization overhead on real world datasets. Experimental results show that the proposed parallelized SGD implementation achieves satisfied scalability and improved execution performance compared with the lock-based approach.

An Opaque Hybrid Transactional Memory

Abstract: The arrival of best-effort hardware transactional memory (TM) creates a challenge for designers of transactional memory runtime libraries. On the one hand, using hardware TM can dramatically reduce the latency of transactions. On the other, it is critical to create a fall-back path to handle the cases where hardware TM cannot complete a transaction, and this path ought to be scalable and reasonably fair to all transactions. Additionally, while the hardwareaccelerated system is likely to have weaker safety guarantees than a pure hardware TM, it ought not to be weaker than what software TM guarantees. We propose a new hybrid TM algorithm based on the “Cohorts” software TM algorithm. Our algorithm guarantees opacity by preventing any transaction from observing the un-committed state of any other transaction. It does so via a novel state machine that maximizes the use of hardware TM, while affording opportunity to enforce fairness policies. We present an implementation of our Hybrid Cohorts that prioritizes transactions that fall back to software mode. In this manner, we ensure that long-running transactions do not starve, while still allowing concurrency among hardware and software transactions.