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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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Dissertation
23 Dec 2011
TL;DR: This thesis makes several contributions in the design and analysis of low-cost HTM systems that yield good performance for any kind of TM program, including a novel mechanism to elegantly manage speculative versions of transactional data by slightly modifying on-chip memory engine.
Abstract: Parallel programming presents an efficient solution to exploit future multicore processors. Unfortunately, traditional programming models depend on programmer’s skills for synchronizing concurrent threads, which makes the development of parallel software a hard and errorprone task. In addition to this, current synchronization techniques serialize the execution of those critical sections that conflict in shared memory and thus limit the scalability of multithreaded applications. Transactional Memory (TM) has emerged as a promising programming model that solves the trade-off between high performance and ease of use. In TM, the system is in charge of scheduling transactions (atomic blocks of instructions) and guaranteeing that they are executed in isolation, which simplifies writing parallel code and, at the same time, enables high concurrency when atomic regions access different data. Among all forms of TM environments, Hardware TM (HTM) systems is the only one that offers fast execution at the cost of adding dedicated logic in the processor. Existing HTMsystems suffer considerable delays when they execute complex transactional workloads, especially when they deal with large and contending transactions because they lack adaptability. Furthermore, most HTM implementations are ad hoc and require cumbersome hardware structures to be effective, which complicates the feasibility of the design. This thesis makes several contributions in the design and analysis of low-cost HTMsystems that yield good performance for any kind of TM program. Our first contribution, FASTM, introduces a novel mechanism to elegantly manage speculative (and already validated) versions of transactional data by slightly modifying on-chip memory engine. This approach permits fast recovery when a transaction that fits in private caches is discarded. At the same time, it keeps non-speculative values in software, which allows in-place x memory updates. Thus, FASTM is not hurt from capacity issues nor slows down when it has to undo transactional modifications. Our second contribution includes two different HTM systems that integrate deferred resolution of conflicts in a conventional multicore processor, which reduces the complexity of the system with respect to previous proposals. The first one, FUSETM, combines different-mode transactions under a unified infrastructure to gracefully handle resource overflow. As a result, FUSETM brings fast transactional computation without requiring additional hardware nor extra communication at the end of speculative execution. The second one, SPECTM, introduces a two-level data versioning mechanism to resolve conflicts in a speculative fashion even in the case of overflow. Our third and last contribution presents a couple of truly flexible HTM systems that can dynamically adapt their underlying mechanisms according to the characteristics of the program. DYNTM records statistics of previously executed transactions to select the best-suited strategy each time a new instance of a transaction starts. SWAPTM takes a different approach: it tracks information of the current transactional instance to change its priority level at runtime. Both alternatives obtain great performance over existing proposals that employ fixed transactional policies, especially in applications with phase changes.

2 citations

Proceedings ArticleDOI
01 Dec 2010
TL;DR: This paper proposes a new type of fine-grained scheme which adds an intermediate locking level and shows that the results showed that the new scheme preserves the scalability and reduces the overhead of Fine-Grained scheme.
Abstract: In a multi-process or multi-thread software trans-actional memory(STM) system, the transactional locking scheme is commonly separated into fine-grained and coarsegrained schemes by protection granularity. In our definition, the protection granularity of fine-grained schemes is varied depending on implementation. Types of protection granularity include per-word, per-object, etc. The coarse-grained scheme is using a global lock for all shared resources. These two types of schemes are preferred under different test environments. The coarse-grained scheme lacks scalability under high contention situation and the fine-grained scheme produces higher overhead than coarse-grained scheme. In this paper, we propose a new type of fine-grained scheme which adds an intermediate locking level. The new scheme separates shared resources into different groups. Groups are organized under the number of executing transactions, and resources are joined to the first accessed transaction group. Thus the overhead of fine-grained scheme is reduced by locking a group of resources. In the experiment of the proposed scheme, the results showed that the new scheme preserves the scalability and reduces the overhead of fine-grained scheme.

2 citations

Journal ArticleDOI
TL;DR: Although precise numbers are lacking, statistics suggest that the number of concurrent programmers has sky-rocketed over the past few years and will continue to do so, mainly from Java's emergence-it's the first ubiquitous concurrent programming language.
Abstract: Although precise numbers are lacking, statistics suggest that the number of concurrent programmers has sky-rocketed over the past few years and will continue to do so. This stems mainly from Java's emergence-it's the first ubiquitous concurrent programming language. The rise in concurrent programmers also reflects an increased use of common C++ multithreaded class libraries and frameworks, Posix pthread library standardization, and other wide spectrum concurrent languages. Although only a small proportion of code found in today's production programs, applications, and systems directly exploits concurrency, every programmer should at least be aware of concurrency.

2 citations

Book ChapterDOI
01 Jan 2018
TL;DR: It is formally prove that CMS complies useless-prefix garbage collection (UP-GC), and on the basis of number of memory accesses for searching consistent version, CMS performs better in comparison with conventional multi-version permissive STM.
Abstract: In this paper, we propose a novel checkpoint-based multi-versioning concurrency control system (CMS) for software transactional memory (STM). A checkpoint is defined to refer a set of versions. CMS maintains a list of live read-only transactions for every checkpoint. An appropriate object versioning technique decides on how many older versions are to be kept or to be removed. Moreover, the proposed method does not require any global synchronization point, such as centralized logical clock for versioning. Due to its efficient garbage-collecting mechanism, CMS is suitable for both read and write-dominated workload. We formally prove that CMS complies useless-prefix garbage collection (UP-GC). On the basis of number of memory accesses for searching consistent version, CMS performs better in comparison with conventional multi-version permissive STM.

2 citations

Book ChapterDOI
01 Jan 2015
TL;DR: The authors are witnessing an increase in the parallel power of computers for the foreseeable future, which requires parallel programming tools and models that can take advantage of the higher number of hardware threads to reach up to high parallelism.
Abstract: We are witnessing an increase in the parallel power of computers for the foreseeable future, which requires parallel programming tools and models that can take advantage of the higher number of hardware threads. For some applications, reaching up to such high parallelism requires going beyond the typical monolithic parallel model: it calls for exposing fine-grained parallel tasks that might exist in a program, possibly nested within memory transactions.

2 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888