Topic
Transactional memory
About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.
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14 Jun 2008
TL;DR: A hardware-assisted memory snapshot is proposed that is built on top of the hardware resources for transactional memory and allows for easy development of system software modules such as concurrent garbage collector and dynamic profiler.
Abstract: We propose a hardware-assisted memory snapshot to improve software concurrency. It is built on top of the hardware resources for transactional memory and allows for easy development of system software modules such as concurrent garbage collector and dynamic profiler.
2 citations
TL;DR: A model for parallel quantum computing in a single ensemble quantum computer using Haskell's software transaction memory, which possesses, besides quantum parallelism, a kind of classical single-instruction-multiple-data parallelism.
2 citations
09 Apr 2018
TL;DR: Current and future safety-critical applications demand fail-operational execution, which requires mechanisms for error recovery, and cycle-by-cycle lockstep execution is unsuitable for energy-efficient heterogeneous multi-cores.
Abstract: Cycle-by-cycle lockstep execution as implemented by current embedded processors is unsuitable for energy-efficient heterogeneous multi-cores, because the different cores are not cycle synchronous. Furthermore, current and future safety-critical applications demand fail-operational execution, which requires mechanisms for error recovery.
2 citations
TL;DR: Memory access instrumentation is fundamental to many applications such as software transactional memory systems, profiling tools and race detectors as mentioned in this paper, and the problem of efficiently instrumenting accesses to memory is examined.
Abstract: Memory access instrumentation is fundamental to many applications such as software transactional memory systems, profiling tools and race detectors. We examine the problem of efficiently instrument...
2 citations
TL;DR: A priority scheduling algorithm is proposed that can not only solve the synchronization obstacles of CMPs, but also almost achieve the same performance as hardware transactional memory systems.
Abstract: Developing a parallel program on Chip multi-processors (CMPs) is a critical and difficult issue. To overcome the synchronization obstacles of CMPs, transactional memory (TM) has been proposed as an alternative control concurrency mechanism, instead of using traditional lock synchronization. Unfortunately, TM has led to seven performance pathologies: DuelingUpgrades, FutileStall, StarvingWriter, StarvingElder, SerializedCommit, RestartConvoy, and FriendlyFire. Such pathologies degrade performance during the interaction between workload and system. Although this performance issue can be solved by hardware, the software solution remains elusive. This paper proposes a priority scheduling algorithm to remedy these performance pathologies. By contrast, the proposed approach can not only solve this issue, but also almost achieve the same performance as hardware transactional memory systems.
2 citations