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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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Patent
20 Aug 2013
TL;DR: A transactional memory (TM) as discussed by the authors is a bank of hardware prework engines, a selectable bank of lookup engines, and a memory unit that stores result values, instructions, and lookup data operands.
Abstract: A transactional memory (TM) includes a selectable bank of hardware algorithm prework engines, a selectable bank of hardware lookup engines, and a memory unit. The memory unit stores result values (RVs), instructions, and lookup data operands. The transactional memory receives a lookup command across a bus from one of a plurality of processors. The lookup command includes a source identification value, data, a table number value, and a table set value. In response to the lookup command, the transactional memory selects one hardware algorithm prework engine and one hardware lookup engine to perform the lookup operation. The selected hardware algorithm prework engine modifies data included in the lookup command. The selected hardware lookup engine performs a lookup operation using the modified data and lookup operands provided by the memory unit. In response to performing the lookup operation, the transactional memory returns a result value and optionally an instruction.

1 citations

Proceedings ArticleDOI
02 May 2015
TL;DR: Hardware Transactional memory performance is application-specific and is dependent on its version management and conflict management configurations, so an adaptive mechanism is needed to adapt its configurations based on multiple application behaviour.
Abstract: Hardware Transactional memory (HTM) performance is application-specific and is dependent on its version management and conflict management configurations. An adaptive mechanism is needed to adapt its configurations based on multiple application behaviour.

1 citations

01 Jan 2008
TL;DR: A new per-directory-line hardware contention management mechanism that allows fairer access between both software and hardware threads without the need to abort any transaction is introduced.
Abstract: Without care, Hardware Transactional Memory presents several performance pathologies that can degrade its performance. Among them, writers of commonly read variables can suffer from starvation. Though different solutions have been proposed for HTM systems, hybrid systems can still suffer from this performance problem, given that software transactions don’t interact with the mechanisms used by hardware to avoid starvation. In this paper we introduce a new per-directory-line hardware contention management mechanism that allows fairer access between both software and hardware threads without the need to abort any transaction. Our mechanism is based on “reserving” directory lines, implementing a limited fair queue for the requests on that line. We adapt the mechanism to the LogTM conflict detection mechanism and show that the resulting proposal is deadlock free. Finally, we sketch how the idea could be applied more generally to reader-writer locks.

1 citations

BookDOI
01 Jan 2014
TL;DR: Concurrency.- Automatically Adjusting Concurrency to the Level of Synchrony.
Abstract: Concurrency.- Automatically Adjusting Concurrency to the Level of Synchrony.- Biological and Chemical Networks.- Speed Faults in Computation by Chemical Reaction Networks.- Fault-Tolerant ANTS.- Task Allocation in Ant Colonies.- Agreement Problems.- Communication-Efficient Randomized Consensus.- Tight Bound on Mobile Byzantine Agreement.- Unbeatable Consensus.- Reliable Broadcast with Respect to Topology Knowledge.- Robot Coordination, Scheduling.- Evacuating Robots via Unknown Exit in a Disk.- Randomized Pattern Formation Algorithm for Asynchronous Oblivious Mobile Robots.- A Theoretical Foundation for Scheduling and Designing Heterogeneous Processors for Interactive Applications.- Graph Distances and Routing.- Vertex Fault Tolerant Additive Spanners.- Close to Linear Space Routing Schemes.- Near-Optimal Distributed Tree Embedding.- Radio Networks.- Deterministic Leader Election in Multi-hop Beeping Networks (Extended Abstract).- Who Are You? Secure Identities in Ad Hoc Networks.- Approximate Local Sums and Their Applications in Radio Networks.- Radio Network Lower Bounds Made Easy.- Shared Memory.- On Correctness of Data Structures under Reads-Write Concurrency.- Solo-Fast Universal Constructions for Deterministic Abortable Objects.- Space Bounds for Adaptive Renaming.- Dynamic and Social Networks Lower Bounds for Structuring Unreliable Radio Networks.- Random Walks on Evolving Graphs with Recurring Topologies.- Randomized Rumor Spreading in Poorly Connected Small-World Networks.- Relativistic Systems.- Making Sense of Relativistic Distributed Systems.- Transactional Memory and Concurrent Data Structures.- Safety of Live Transactions in Transactional Memory: TMS is Necessary and Sufficient.- Decomposing Opacity.- The Adaptive Priority Queue with Elimination and Combining.- Improving Average Performance by Relaxing Distributed Data Structures.- Distributed Graph Algorithms.- Almost-Tight Distributed Minimum Cut Algorithms.- Distributed Algorithms for Coloring Interval Graphs.- Distributed Symmetry Breaking in Hypergraphs.- Communication.- On Streaming and Communication Complexity of the Set Cover Problem.- On the Communication Complexity of Linear Algebraic Problems in the Message Passing Model.- Near-Constant-Time Distributed Algorithms on a Congested Clique.- Brief Announcement: Replacement - Handling Failures in a Replicated State Machine.- Brief Announcement: The Power of Scheduling-Aware Synchronization.- Brief Announcement: Assignment of Different-Sized Inputs in MapReduce.- Brief Announcement: Scheduling Multiple Objects in Distributed Transactional Memory.- Brief Announcement: Relaxing Opacity in Pessimistic Transactional Memory.- Brief Announcement: A Practical Transactional Memory Interface.- Brief Announcement: On Dynamic and Multi-functional Labeling Schemes.- Brief Announcement: Update Consistency in Partitionable Systems.- Brief Announcement: Breaching the Wall of Impossibility Results on Disjoint-Access Parallel TM.- Brief Announcement: COP Composition Using Transaction Suspension in the Compiler.- Brief Announcement: Non-blocking Monitor Executions for Increased Parallelism.- Brief Announcement: Agreement in Partitioned Dynamic Networks.- Brief Announcement: The 1-2-3-Toolkit for Building Your Own Balls-into-Bins Algorithm.- Brief Announcement: k-Selection and Sorting in the SINR Model.- Brief Announcement: Distributed 3/2-Approximation of the Diameter.- Brief Announcement: Space-Optimal Silent Self-stabilizing Spanning Tree Constructions Inspired by Proof-Labeling Schemes.- Brief Announcement: Secure Anonymous Broadcast.- Brief Announcement: Privacy-Preserving Location-Based Services.

1 citations

Proceedings ArticleDOI
26 Feb 2018
TL;DR: The result shows that those techniques can enhance averagely 117% / 140% transaction performance and aim to reduce persistent overhead as many as possible.
Abstract: Non-volatile memory is emerged such as PCM and 3D XPoint. With the advent of Non-volatile memory, Software platforms have also been developed to manage Non-volatile memory areas. Recently those platforms support PTM system(Persistent transactional memory) which provides transaction system and guarantee crash-consistency of transaction at the main memory level. For ensuring crash-consistency of transaction, PTM system should use frequently hardware-instruction. Because ensuring persistent boundary has been changed volatile memory/storage to volatile cache/Non-volatile memory. This has a huge adverse effect on PTM system. In this paper, we propose a three techniques. Append-only dynamic log can support compact and dynamic log area. Lazy and bulk persistence aggressively delay persistence phase to commit phase. Non temporal persistence can provide enhanced memory copy function. Above techniques aim to reduce persistent overhead as many as possible. Our result shows that those techniques can enhance averagely 117% / 140% transaction performance.

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888