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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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Book ChapterDOI
22 Nov 2007
TL;DR: A new general transaction iteration's data reusing (TItDR) method which reuses the opened object of failed transaction in the following re-execution, which greatly simplify the opening process if it has been opened in previous failed transaction and most of the cleanup work are no longer needed.
Abstract: Transactional Memory (TM) has been the promising parallel programming technique to relieve the tedious work of synchronizing shared object using lock mechanism. Transaction execution required to be atomic and isolated relative to the whole system. The transaction fails if found violated access to the shared object from other transaction, and it will be re-executed till finally commit successfully; currently, most TM systems are required to restore shared memory's state before reexecution, this cleanup cost and the shared object's opening cost greatly hurdle system's performance. In this paper, we propose a new general transaction iteration's data reusing (TItDR) method which reuses the opened object of failed transaction in the following re-execution. The obvious advantage is that it greatly simplify the opening process if it has been opened in previous failed transaction and most of the cleanup work are no longer needed. TItDR leaves opened object in pseudo-active state and restart the transaction, We talk about conflicts resolution, validation, commit/abort processing problem along with our data reusing method and show that TItDR will not incur more conflicts and more overhead for validation or commit. Both currently proposed software transactional memory (STM) systems and hardware systems (HTM) have much potential data reusing. Our test result is based on STM implementation, which shows 40% performance improvement on average.

1 citations

Patent
11 Jul 2014
TL;DR: In this paper, techniques for generating a multi-transactional system using transactional memory techniques are described. But the TM logs for completed transactions are used for error detection and recovery and maintaining high availability of the device.
Abstract: Techniques are disclosed for generating a multi-transactional system using transactional memory techniques. According to certain embodiments, a device may include a memory, one or more processing entities, and a transactional memory system for maintaining a plurality of transactional memory (TM) logs in a first portion of the memory. Each TM log may be associated with one transaction from a plurality of transactions sequentially executed by the one or more processing entities and each transaction comprises a plurality of operations. Furthermore, each TM log associated with each transaction comprises information associated with changes to a second portion of the memory caused by execution of operations from the transaction using the one or more processing entities. The TM logs for completed transactions may be used for error detection and recovery and maintaining high availability of the device.

1 citations

Patent
04 Feb 2014
TL;DR: In this article, the authors present a transactional memory block in a memory of a web hosting server on the NID that stores configuration information that configures the corresponding virtual NID.
Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. For each virtual NID there is a block in a memory of a transactional memory on the NID. This block stores configuration information that configures the corresponding virtual NID. The NID also has a single managing processor that monitors configuration of the plurality of virtual NIDs. If there is a write into the memory space where the configuration information for the virtual NIDs is stored, then the transactional memory detects this write and in response sends an alert to the managing processor. The size and location of the memory space in the memory for which write alerts are to be generated is programmable. The content and destination of the alert is also programmable.

1 citations

Book
07 Aug 2019
TL;DR: Transactional memory (TM), a new programming paradigm, is one of the latest approaches to write programs for next generation multicore and multiprocessor systems.
Abstract: Transactional memory (TM), a new programming paradigm, is one of the latest approaches to write programs for next generation multicore and multiprocessor systems. TM is an alternative to lock-based ...

1 citations

Proceedings ArticleDOI
25 Jun 2012
TL;DR: New hardware support for enforcing isolation of critical section execution can detect and tolerate races, allowing programs to execute race-free, and focuses on enhancing the reliability of existing lock-based programs.
Abstract: When lock-based parallel programs execute on conventional multi-core hardware, faulty software can cause hard-to-debug race conditions in critical sections that violate the contract between locks and their protected shared variables. This paper proposes new hardware support for enforcing isolation of critical section execution. It can detect and tolerate races, allowing programs to execute race-free. Our hardware scheme targets the existing large code base of locked-based parallel programs written in type unsafe languages such as C and C++. Our approach works directly on unmodified executables. An evaluation of 13 programs from the SPLASH2 and PARSEC suites shows that the cost of the additional hardware and the impact on the overall execution time is minimal for these applications. Our mechanism is complementary to hardware transactional memory in that it uses similar structures but focuses on enhancing the reliability of existing lock-based programs.

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888