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Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.


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Proceedings ArticleDOI
01 Jul 2013
TL;DR: This paper proposes two methods to restrain the occurrence of very harmful conflicts in TM, one relieves starving writers who will keep stalling for a long time and the other serially executes highly conflicted transactions which tend to abort repeatedly.
Abstract: Lock-based thread synchronization techniques have been commonly used in parallel programming on multi-core processors. However, lock can cause deadlocks and poor scalabilities. Hence, transactional memory has been proposed and studied for lock-free synchronization. However, the performance can decline with some conflict patterns in TM. Therefore, this paper proposes two methods to restrain the occurrence of very harmful conflicts. The one relieves starving writers who will keep stalling for a long time. The other serially executes highly conflicted transactions which tend to abort repeatedly. The result of the experiment shows that the merged model of these two methods improves the performance 72.2% in maximum and 28.4% in average.

1 citations

01 Jan 2014
TL;DR: The results indicate a strong influence of the allocators on the overall performance and point to the importance of reporting the allocator utilized in the performance evaluation of transactional memory systems, as the conclusions might change from one allocator to another.
Abstract: Although dynamic memory management accounts for a significant part of the execution time on many modern software systems, its impact on the performance of transactional memory systems has been mostly overlooked. In order to shed some light into this subject, this paper reports our first attempt at evaluating the effects of memory allocators on the performance of transactional applications. In general, our results indicate a strong influence of the allocators on the overall performance. In particular, we observed differences ranging from 4% to 171% in the STAMP applications. Our results point to the importance of reporting the allocator utilized in the performance evaluation of transactional memory systems, as the conclusions might change from one allocator to another.

1 citations

Proceedings ArticleDOI
27 Sep 2015
TL;DR: It is shown that the verification of coherence for parameterized cache protocols with filters can be reduced to systems with only a finite number of cache lines, and the method is implemented and used to verify transactional memory coherence protocols with respect to different conflict resolution policies.
Abstract: We address the problem of parameterized verification of cache coherence protocols for hardware accelerated transactional memories. In this setting, transactional memories leverage on the versioning capabilities of the underlying cache coherence protocol. The length of the transactions, their number, and the number of manipulated variables (i.e., cache lines) are parameters of the verification problem. Caches in such systems are finite-state automata communicating via broadcasts and shared variables. We augment our system with filters that restrict the set of possible executable traces according to existing conflict resolution policies. We show that the verification of coherence for parameterized cache protocols with filters can be reduced to systems with only a finite number of cache lines. For verification, we show how to account for the effect of the adopted filters in a symbolic backward reachability algorithm based on the framework of constrained monotonic abstraction. We have implemented our method and used it to verify transactional memory coherence protocols with respect to different conflict resolution policies.

1 citations

Proceedings ArticleDOI
18 Apr 2011
TL;DR: The experimental results show that the proposed speculative multi-threading model based on transactional memory is competent to exploit the speculative thread-level parallelism with little parallel degree loss by the parallel & ordered transaction partition strategy.
Abstract: Thread level speculation (TLS) and Transactional memory (TM) are both promising way to enhance the performance of chip multiprocessor (CMP). The complexity of providing efficient memory accesses buffering mechanism in TLS can be supported by TM logically. This paper proposes a speculative multi-threading model based on transactional memory, including its special hardware, compiler and execution support. It's a low-design-complexity approach to effective unified support for both TLS&TM. The experimental results show that our framework is competent to exploit the speculative thread-level parallelism with little parallel degree loss by the parallel & ordered transaction partition strategy.

1 citations

Proceedings ArticleDOI
04 Jul 2011
TL;DR: The underlying product line development process, TMPL's structure, and an early quantitative evaluation of the FPGA-based implementation of the TMPL implementation are presented.
Abstract: Transactional memory is regarded as a very promising technology to deal with concurrency control in future multicore and manycore systems. While a lot of software, hardware, and hybrid transactional memory implementations have been proposed and analyzed, the silver bullet still hasn't been found. The main reason is that the performance of transactional memory significantly depends on the actual application scenario. TMPL is a product line of transactional memory implementations for configurable hardware platforms, mainly aimed at the domain of embedded systems. It facilitates the derivation of various kinds of transactional memory with a large variety of strategies for conflict detection, conflict resolution, and versioning, from a common platform. Thereby, developers can experiment with different strategies and select one that is most efficient for a given workload profile. This paper presents the underlying product line development process, TMPL's structure, and an early quantitative evaluation of our FPGA-based implementation.

1 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202316
202240
202129
202063
201970
201888