Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

The Teleportation Design Pattern for Hardware Transactional Memory

Abstract: We identify a design pattern for concurrent data structures, called teleportation, that uses best- effort hardware transactional memory to speed up certain kinds of legacy concurrent data struc- tures. Teleportation unifies and explains several existing data structure designs, and it serves as the basis for novel approaches to reducing the memory traffic associated with fine-grained locking, and with hazard pointer management for memory reclamation.

Hardware/hybrid transactional memory

Abstract: Transactional memory(TM) systems become considerable popular due to it simplifying the development of highly scalable parallel programs. The implementations of TM systems are classified into three types: hardware transactional memory (HTM), software transactional memory (STM) and hybrid transactional memory (HyTM). We analyze and compare some typical HTM and HyTM from version management, detection management, nested transaction, isolated, etc. In addition, we discuss LogTM Signature Edition (LogTM-SE) system from eager version management, eager conflict detection, memory paging, thread switching and closed/open nested transaction.

The Transactional Conflict Problem

Abstract: The transactional conflict problem arises in transactional systems whenever two or more concurrent transactions clash on a data item. While the standard solution to such conflicts is to immediately abort one of the transactions, some practical systems consider the alternative of delaying conflict resolution for a short interval, which may allow one of the transactions to commit. The challenge in the transactional conflict problem is to choose the optimal length of this delay interval so as to minimize the overall running time penalty for the conflicting transactions. In this paper, we propose a family of optimal online algorithms for the transactional conflict problem. Specifically, we consider variants of this problem which arise in different implementations of transactional systems, namely "requestor wins" and "requestor aborts" implementations: in the former, the recipient of a coherence request is aborted, whereas in the latter, it is the requestor which has to abort. Both strategies are implemented by real systems. We show that the requestor aborts case can be reduced to a classic instance of the ski rental problem, while the requestor wins case leads to a new version of this classical problem, for which we derive optimal deterministic and randomized algorithms. Moreover, we prove that, under a simplified adversarial model, our algorithms are constant-competitive with the offline optimum in terms of throughput. We validate our algorithmic results empirically through a hardware simulation of hardware transactional memory (HTM), showing that our algorithms can lead to non-trivial performance improvements for classic concurrent data structures.

New hardware support transactional memory and parallel debugging in multicore processors

Abstract: In the multicore era, parallel programming is become a must for programmers. However, parallel programming is intrinsically not intuitive and prone to errors. To face these drawbacks, it have arisen new tools to make this task easier by providing new parallel programming models and new debugging tools. Usually, all this new tools are not trivial, some of then require speculation or other complex mechanisms, which forces, in many cases, to add hardware support to achieve a reasonable performance. Among the hardware resources for accelerating these kind of tools, one of the most generally used in research papers, and therefore, with a lot of potential to be included in future general purpose processors, are signatures. A signature is a fixed piece of hardware that can host an unbounded number of addresses (using hash functions and allowing aliasing) in their storage elements, and it can check if a particular address was stored previously in the signature. This thesis contributes to the area of parallel programming hardware support by introducing new hardware elements in multicore processors, with the aim to accelerate an optimize new tools, abstractions and applications related with parallel programming in multicore processors, such as transactional memory and data race detectors. Specifically, we set up a Hardware Transactional Memory (HTM) system where signatures are part of the hardware support and we develop a new hardware filter based in minor modifications of the hardware, that allows to considerably reduce the signature size either their false positive rate (we call this filter CFM-TM). Under certain circumstances, the performance of the system it is also significantly improved. We also build the first hardware asymmetric data race detector (which also tolerates these races), called Pacman. Asymmetric data races are a very common type of data race that may cause dangerous concurrent bugs, and that until this work, it was explored only as a software approach. The hardware support of our detector is based on a centralized module of hardware signatures. We demonstrate that Pacman introduces negligible slowdowns in the system, and that it is able to efficiently detect and tolerate asymmetric data races. Finally, we propose a novel hardware signature module (called FlexSig) that solves some of the problems that we found when building our previous tools for multicore architectures based on signatures. Specifically, we design a signature module that can host a big number of signatures when there is a high demand of signatures, and also it can achieve a very low false positive rate when the demand of signatures is modest. We explore several strategies to allocate signatures in FlexSig to adapt to the different characteristics of the tools and applications that uses them. Concluding, we optimized the use of signatures in a HTM system introducing our CFM-TM filter, we develop a new debugging tool with signatures as main hardware support, and we build a new hardware signature module that allows a great flexibility in the size and number of allocated signatures, which fits in real scenario represented by a general purpose multicore processor executing a wide range of signature-demanding applications and tools.