Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Lower bounds for Transactional memory

Abstract: Transactional memory allows the user to declare sequences of instructions as speculative transactions that can either commit or abort. If a transaction commits, it appears to be executed sequentially, so that the committed transactions constitute a correct sequential execution. If a transaction aborts, none of its update operations can aect other transactions. The TM implementation endeavors to execute these instructions in a manner that eciently utilizes the concurrent computing facilities provided by multicore architectures. The TM abstraction, in its original manifestation, extended the processor’s instruction set with instructions to indicate which memory accesses must be transactional. Most popular TM designs, subsequent to the original proposal have implemented all the functionality in software. More recently, processors have included hardware extensions to support small transactions. Hardware transactions may be spuriously aborted due to several reasons: cache capacity overflow, interrupts etc. This has led to proposals for hybrid TMs in which the fast, but potentially unreliable hardware transactions are complemented with slower, but more reliable software transactions. The complexity of TM implementations, whether realized in hardware or software, is characterized by several measures: ordering semantics for transactions, conditions under which transactions must terminate, conditions under which transactions must commit/abort, bound on the number of versions that can be maintained, choice of the complexity metric and complexity of read-only or updating transactions as well as a multitude of other implementation strategies. In this work, we survey known complexity bounds for implementing TM as a shared object and the implicit assumptions underlying these results.

Featherweight transactions: decoupling threads and atomic blocks

Abstract: Note: 1229453 Reference EPFL-CONF-192836doi:10.1145/1229428.1229453 Record created on 2013-12-23, modified on 2017-05-12

Using Formal Methods to Verify Transactional Abstract Concurrency Control

Abstract: USING FORMAL METHODS TO VERIFY TRANSACTIONAL ABSTRACT CONCURRENCY CONTROL

Efficient Concurrent Range Queries in B+-trees using RCU-HTM

Abstract: In this work, we exploit RCU-HTM, a synchronization mechanism that combines Read-Copy-Update (RCU) and Hardware Transactional Memory (HTM) to support linearizable and highly efficient range queries in a concurrent B+-tree. Range queries in our B+-tree start with an asynchronized traversal and then perform a horizontal scan of leaf nodes, by following sibling pointers, using hardware transactions. Despite its simplicity, our RCU-HTM based B+-tree with range query support greatly outperforms state-of-the-art map data structures for range queries in several execution scenarios.

Apparatus and method for reentering a transactional sequence with hardware transactional memory

Abstract: An apparatus and method are described for reentering a transactional sequence for hardware transactional memory For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; execution circuitry within at least one of the cores to execute a transactional sequence of instructions; a mask value to identify a specified set of architectural state to be saved upon reaching a particular instruction within the transactional sequence of instructions; and a scratchpad memory within the execution circuitry to store the specified set of architectural state upon reaching the particular instruction within the sequence of instructions