Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Operation-Level Wait-Free Transactional Memory with Support for Irrevocable Operations

Abstract: Transactional memory (TM) aims to be a general purpose concurrency mechanism. However, operations which cause side-effects cannot be easily managed by a TM system, in which transactions are executed optimistically. In particular, networking, I/O, and some system calls cannot be executed within a transaction that may abort and restart (e.g., due to conflicts). Thus, many TM systems let transactions become irrevocable, i.e., they are guaranteed to commit. Supporting this in TM is a challenge, but there exist fast and highly parallel TM systems that allow for irrevocable transactions. However, no such system so far provides guarantees that all transactional operations terminate in a finite time. In this paper, we show that support for irrevocable operations does not entail inherent waiting. We present a TM algorithm that guarantees wait-freedom for any transactional operation. The algorithm is based on the weakest synchronization primitive possible (test-and-set), and guarantees opacity and strong progressiveness. To experimentally evaluate the algorithm, we developed a proof-of-concept TM system and tested it using the STMBench7 benchmark.

Achieving Starvation-Freedom in Multi-Version Transactional Memory Systems

Abstract: Software Transactional Memory systems (STMs) have garnered significant interest as an elegant alternative for addressing synchronization and concurrency issues with multi-threaded programming in multi-core systems. Client programs use STMs by issuing transactions. STM ensures that transaction either commits or aborts. A transaction aborted due to conflicts is typically re-issued with the expectation that it will complete successfully in a subsequent incarnation. However, many existing STMs fail to provide starvation freedom, i.e., in these systems, it is possible that concurrency conflicts may prevent an incarnated transaction from committing. To overcome this limitation, we systematically derive a novel starvation free algorithm for multi-version STM. Our algorithm can be used either with the case where the number of versions is unbounded and garbage collection is used or where only the latest K versions are maintained, KSFTM. We have demonstrated that our proposed algorithm performs better than existing state-of-the-art STMs.

Proceedings of the 2006 workshop on Memory system performance and correctness

Abstract: We are pleased to present the proceedings of the 2006 Workshop on Memory Systems Performance and Correctness (MSPC 2006). MSPC focuses on improving the memory system performance and correctness of general-purpose programs. MSPC continues the successful series of Memory Systems Performance workshops held in 2002 (Berlin), 2004 (Washington, DC), and 2005 (Chicago). This year, the steering committee decided to add a correctness aspect to the workshop. This multi-disciplinary workshop fosters collaboration among researchers in a range of fields including compilers, memory management, programming languages, architecture, operating systems, performance evaluation, and database systems.MSPC 2006 solicited papers on all aspects of memory system performance and correctness. We received twenty-seven submissions. Each paper received three reviews from the program committee. The program committee met on September 5 via teleconference and selected the eleven papers in these proceedings. The final program contains papers covering a broad range of topics, including traditional topics such as cache design and garbage collection, as well as new topics such as memory models for transactional memory and memory management techniques for improving reliability. In addition to the papers, we are fortunate to include a keynote talk from David Wood on the memory systems challenges of multi-core processors.

Energy Efficiency of Software Transactional Memory in a Heterogeneous Architecture

Abstract: Hardware vendors make an important effort creating low-power CPUs that keep battery duration and durability above acceptable levels. In order to achieve this goal and provide good performance-energy for a wide variety of applications, ARM designed the big.LITTLE architecture. This heterogeneous multi-core architecture features two different types of cores: big cores oriented to performance, fast and power-hungry, and little cores, slower and aimed to save energy consumption. As all the cores have access to the same memory, multi-threaded applications must resort to some mutual exclusion mechanism to coordinate the access to shared data by the concurrent threads. Transactional Memory (TM) represents an optimistic approach for shared-memory synchronization. To take full advantage of the features offered by software TM, but also benefit from the characteristics of the heterogeneous big.LITTLE architectures, our focus is to propose TM solutions that take into account the power/performance requirements of the application and what it is offered by the architecture. In order to understand the current state-of-the-art and obtain useful information for future power-aware software TM solutions, we have performed an analysis of a popular TM library running on top of an ARM big.LITTLE processor. Experiments show, in general, better scalability for the LITTLE cores for most of the applications except for one, which requires the computing performance that the big cores offer.

WFR-TM: Wait-Free Readers without Sacrificing Speculation of Writers

Abstract: Transactional Memory (TM) is a promising concurrent programming paradigm which employs transactions to achieve synchronization in accessing common data known as transactional variables A transaction may either commit by making its updates to transactional variables visible or abort by discarding all its changes