Topic
Transactional memory
About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.
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01 Jan 2013
TL;DR: A fault-tolerant Lu algorithm is proposed for this transactionalize Lu algorithm that uses the data-versioning mechanism of the transactional memory system, detects errors based on transactions and recovers the error by rolling back the error transaction.
Abstract: With the popularization of multi-core processors, transaction memory, as a concurrent control mechanism with easy programing and high scalability, has attracted more and more attention. As a result, the reliability problems of transactional memory become a concerning issue. This paper addresses a transactional implementation of the Lu benchmark of SPLASH-2, and proposes a fault-tolerant Lu algorithm for this transactionalize Lu algorithm. The fault-tolerant Lu uses the data-versioning mechanism of the transactional memory system, detects errors based on transactions and recovers the error by rolling back the error transaction. The experiments show that the fault-tolerant Lu can get a better fault tolerance effect under a smaller cost.
Patent•
12 Aug 2009
TL;DR: In this paper, the threads share a common view of the memory of the system and are suspended in order to allow a block of instructions to execute atomically, all but one of the threads are suspended.
Abstract: Threads are executed concurrently in a computer system. They may be executed on separate processors or on a single processor with hardware support for simultaneous multithreading (SMT). The threads share a common view of the memory of the system. In order to allow a block of instructions to execute atomically, all but one of the threads are suspended. The threads may be suspended by writing a predefined value to a specified memory location. This may cause an interrupt, which suspends the threads. The threads may be suspended in response to a user level instruction. The processor may include hardware to support transactional memory, such as a buffer to store write data and an area to store read addresses.
Patent•
14 Jun 2013TL;DR: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction as mentioned in this paper.
Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort Other embodiments are described and claimed
19 Sep 2012
TL;DR: In Transactional Memory (TM), a conflict occurs when a memory block is accessed concurrently by two or more transactions and at least one of them is a write access.
Abstract: In Transactional Memory (TM), a conflict occurs when a memory block is accessed concurrently by two or more transactions and at least one of them is a write access. The management of conflicts significantly impacts TM performance. There are two alternative approaches for managing conflicts: Reactive Contention Management (RCM) [1] and Proactive Contention Management (PCM) [2]. Previous contention management schemes treat all transactions with no weights, and make a decision based on the information provided by the running transaction instance.
TL;DR: This paper proposes a transaction execution model to improve GPU hardware utilization and perform synchronization among transactions, and optimize the indexing data structures that used extensively in OLTP systems for fast storing on GPUs.