Transactional memory

About: Transactional memory is a research topic. Over the lifetime, 2365 publications have been published within this topic receiving 60818 citations.

Memory models for open-nested transactions

Abstract: Open nesting provides a loophole in the strict model of atomic transactions. Moss and Hosking suggested adapting open nesting for transactional memory, and Moss and a group at Stanford have proposed hardware schemes to support open nesting. Since these researchers have described their schemes using only operational definitions, however, the semantics of these systems have not been specified in an implementation-independent way. This paper offers a framework for defining and exploring the memory semantics of open nesting in a transactionl-memory setting.Our framework allows us to define the traditional model of serializability and two new transactional-memory models, race freedom and prefix race freedom. The weakest of these memory models, prefix race freedom, closely resembles the Stanford openesting model. We prove that these three memory models are equivalent for transactional-memory systems that support only closed nesting, as long as aborted transactions are "ignored." We prove that for systems that support open nesting, however, the models of serializability, race freedom, and prefix race freedom are distinct. We show that the Stanford TM system implements a model at least as strong as prefix race freedom and strictly weaker than race freedom. Thus, their model compromises serializability, the property traditionally used to reason about the correctness of transactions.

Identifying the optimal level of parallelism in transactional memory applications

Abstract: In this paper we investigate the issue of automatically identifying the "natural" degree of parallelism of an application using software transactional memory (STM), i.e., the workload-specific multiprogramming level that maximizes application's performance. We discuss the importance of adapting the concurrency level in two different scenarios, a shared-memory and a distributed STM infrastructure. We propose and evaluate two alternative self-tuning methodologies, explicitly tailored for the considered scenarios. In shared-memory STM, we show that lightweight, black-box approaches relying solely on on-line exploration can be extremely effective. For distributed STMs , we introduce a novel hybrid approach that combines model-driven performance forecasting techniques and on-line exploration in order to take the best of the two techniques, namely enhancing robustness despite model's inaccuracies, and maximizing convergence speed towards optimum solutions.

Thread-Level Transactional Memory

Abstract: This paper presents thread-level transactional memory (TTM), a memory system interface that separates the semantics of transactions—atomicity, consistency, and isolation—from the implementation. By making transactions a thread-level abstraction, TTM permits implementations using different combinations of of high-level software, low-level software, and dedicated hardware. TTM tracks a transaction’s read and write sets and creates a "before-image" log in the thread’s virtual address space. We evaluate four TTM implementations—broadcast and directory coherence times two different transaction abort mechanisms—using full-system simulation. Like previous transactional memory systems, TTM implementations are competitive with or better than lock-based synchronization. TTM’s ability to cache the before and after images both supports large transactions and enables low memory bandwidth on successful commits and fast rollback on aborts.

Pisces: A Scalable and Efficient Persistent Transactional Memory

Abstract: Persistent transactional memory (PTM) programming model has recently been exploited to provide crashconsistent transactional interfaces to ease programming atop NVM. However, existing PTM designs either incur high reader-side overhead due to blocking or long delay in the writer side (efficiency), or place excessive constraints on persistent ordering (scalability). This paper presents Pisces, a read-friendly PTM that exploits snapshot isolation (SI) on NVM. The key design of Pisces is based on two observations: the redo logs of transactions can be reused as newer versions for the data, and an intuitive MVCC-based design has read deficiency. Based on the observations, we propose a dual-version concurrency control (DVCC) protocol that maintains up to two versions in NVMbacked storage hierarchy. Together with a three-stage commit protocol, Pisces ensures SI and allows more transactions to commit and persist simultaneously. Most importantly, it promises a desired feature: hiding NVM persistence overhead from reads and allowing nearly non-blocking reads. Experimental evaluation on an Intel 40-thread (20-core) machine with real NVM equipped shows that Pisces outperforms the state-of-the-art design (i.e., DUDETM) by up to 6.3× for micro-benchmarks and 4.6× for TPC-C new order transaction, and also scales much better. The persistency cost is from 19% to 50% for 40 threads.

Optimizations for an unbounded transactional memory (utm) system

Abstract: A method and apparatus for optimizing an Unbounded Transactional Memory (UTM) system is herein described. Hardware support for monitors, buffering, and metadata is provided, where orthogonal metaphysical address spaces for metadata may be separate associated with threads and/or software subsystems within threads. In addition, the metadata may be held with hardware in a compressed manner with regard to data transparently to software. Furthermore, in response to metadata access instruction/operations the hardware is capable of supporting a forced metadata value to enable multiple modes of transactional execution. However, if monitors, buffered data, metadata, or other information is lost or conflicts are detected hardware provides for variations of a loss instruction that is able to poll a transaction status register for such loss or conflict and jump execution to a label in response to detecting the loss or conflict. Similarly, multiple variations of a commit instruction are provided for to allow software to define commit conditions and information to clear upon commit. Furthermore, hardware provides support to enable suspension and resume of transactions upon ring level transitions.